74LVC2G34GW,125

双缓冲器

The is a dual Buffer Gate fully specified for partial power-down applications using IOFF. Inputs can be driven from either 3.3/5V devices. These features allow the use of these devices in a mixed 3.3 and 5V environment. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

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High noise immunity

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CMOS low-power consumption

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Direct interface with TTL levels

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Complies with JEDEC standard

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5V Tolerant input/output for interfacing with 5V logic

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Latch-up performance exceeds 250mA

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±24mA Output drive