XCKU035 3FFVA1156E 磨码
* Up to 1.2M logic cells leveraging 2nd generation 3D IC * Multi-chip integration for DSP-intensive applications * Multiple integrated PCI-Express Gen3 cores * 8.2 TeraMACs of DSP compute performance * Up to two speed-grade improvement with high utilization * 16G backplane-capable transceivers, up to 64 per device * 2,400 Mb/s DDR4 for robust operation over varying PVT * System integration reduces application BOM cost by up to 60% * 12.5 Gb/s transceivers in slowest speed grade * 2,400 Mb/s DDR4 in a mid-speed grade * VCXO integration reduces clocking component cost * Up to 40% lower power vs. previous generation * Fine granular clock gating with UltraScale ASIC-like clocking * Enhanced logic cell packing reduces dynamic power * Footprint compatibility with Virtex UltraScale for scalability * Co-optimized with Vivado Design Suite for rapid design closure
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|---|---|---|
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