SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 7.5ns 100Pin TQFP
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single R/W Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * /CKE pin to enable clock and suspend operation * JEDEC 100-pin QFP * Power supply: Vdd 3.3V ± 5%, Vddq 3.3V/2.5V ± 5% * JTAG Boundary Scan for BGA packages * Commercial and Industrial temperature support * Lead-free available * Error Detection and Error Correction
| 型号 | 品牌 | 下载 |
|---|---|---|
| IS61NLF12836A-7.5TQI | Integrated Silicon SolutionISSI | 下载 |
| IS61LV256AL-10TL | Integrated Silicon SolutionISSI | 下载 |
| IS61WV6416BLL-12TL | Integrated Silicon SolutionISSI | 下载 |
| IS61C1024-15J | Integrated Silicon SolutionISSI | 下载 |
| IS61LV256-15T | ICSI 矽成 | 下载 |
| IS61C1024AL-12TI | Integrated Silicon SolutionISSI | 下载 |
| IS61C6416AL-12TI | Integrated Silicon SolutionISSI | 下载 |
| IS61LV6416-10TI | Integrated Silicon SolutionISSI | 下载 |
| IS61WV25616BLL-10BI-TR | Integrated Silicon SolutionISSI | 下载 |
| IS61WV25616BLL-10BI | Integrated Silicon SolutionISSI | 下载 |
| IS61WV5128BLL-10BI | Integrated Silicon SolutionISSI | 下载 |