74F112PC

双JK负边沿触发触发器 Dual JK Negative Edge-Triggered Flip-Flop

The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#

D

or C#

D

prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#

D

and C#

D

force both Q and Q# HIGH