CDC2582PAH

3.3 -V锁相环时钟差分LVPECL时钟输入驱动器 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

description

The CDC2582 is a high-performance, low-skew, low-jitter clock driver.

Low Output Skew for Clock-Distribution and Clock-Generation Applications

Operates at 3.3-V VCC

Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs

Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency

No External RC Network Required

External Feedback Input FBIN Is Used to Synchronize the Outputs With the Clock Inputs

Application for Synchronous DRAMs

Outputs Have Internal 26-Ω Series Resistors to Dampen Transmission-Line Effects

State-of-the-Art EPIC-ΙΙBBiCMOS Design Significantly Reduces Power Dissipation

Distributed VCC and Ground Pins Reduce Switching Noise

Packaged in 52-Pin Quad Flatpack