MC10EP131

3.3V / 5V ECL四D触发器与设置，复位和差分时钟 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

The is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.Each flip-flop may be clocked separately by holding Common Clock Cbar HIGH, then using the Clock Enable inputs for clocking CCommon clocking is achieved by holding the Cbar inputs HIGH while using the differential common clock C to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.Individual asynchronous resets R and an asynchronous set SET are provided.Data enters the master when both C are LOW, and transfers to the slave when either CThe 100 Series contains temperature compensation.

Features

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460ps Typical Propagation Delay

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Maximum Frequency > 3 GHz Typical

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Differential Individual and Common Clocks

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Individual Asynchronous Resets

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Asynchronous Set

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PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V

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Open Input Default State

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Safety Clamp on Inputs

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Q Output will default LOW with inputs open or at VEE

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Pb-Free Packages are Available