CY2304SXC-1

CYPRESS SEMICONDUCTOR  CY2304SXC-1  芯片, 零延时缓冲器 3.3V

The is a Zero Delay Buffer designed to distribute high-speed clocks in PC and workstation. The part has an on-chip phase-locked loop PLL that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250ps and output-to-output skew is guaranteed to be less than 200ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25µA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500ps. The CY2304-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path.

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Zero input-output propagation delay, adjustable by capacitive load on FBK input

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Multiple configurations

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Multiple low-skew outputs

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90ps Typical peak cycle-to-cycle jitter at 15pF/66MHz