SN74LVC1G139DCUT

TEXAS INSTRUMENTS  SN74LVC1G139DCUT  逻辑芯片, 2-4线译码器, 8SOIC

The is a 2-to-4 Decoder designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Supports down translation to VCC

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Ioff Supports live insertion, partial-power-down mode and back-drive protection

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Latch-up performance exceeds 100mA per JESD 78, class II

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10µA Maximum low power consumption

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±24mA Output drive at 3.3V

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Green product and no Sb/Br