EPM7064STC44-10N

ALTERA  EPM7064STC44-10N  芯片, 可编程逻辑器件 MAX ISP PLD

The is a high-density, high-performance Programmable Logic Device PLD based on second-generation MAX® architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules LPM, Verilog HDL, VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys and VeriBest.

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Built-in JTAG boundary-scan test

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PCI-compliant devices available

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5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies

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Open-drain output option

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Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls

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Programmable power-saving mode for a reduction of over 50% in each macrocell

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Six pin or logic-driven output enable signals

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Two global clock signals with optional inversion

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Enhanced interconnect resources for improved routability

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Programmable output slew-rate control