SRAM Chip Async Dual 5V 8Kbit 1K x 8 25ns 52Pin PLCC T/R
* True dual-ported memory cells, which allow simultaneous reads of the same memory location * 1 K / 2 K × 8 organization * 0.35 micron complementary metal oxide semiconductor CMOS for optimum speed and power * High speed access: 15 ns * Low operating power: ICC = 110 mA typical, Standby: ISB3 = 0.05 mA typical * Fully asynchronous operation * Automatic power-down * BUSY output flag to indicate access to the same location by both ports * INT/ flag for port-to-port communication * Available in 52-pin plastic leaded chip carrier PLCC, 52-pin plastic quad flat package PQFP * Pb-free packages available
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|---|---|---|
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