MT48LC8M16A2P-7E:L

MICRON  MT48LC8M16A2P-7E:L  芯片, 存储器, SDRAM, 128MB, 133MHZ, 54TSOP

The MT48LC8M16A2P-7E is a SDR SDRAM with high-speed CMOS and uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed and random-access operation. This is a high-speed CMOS, dynamic random-access memory containing 134217728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface. Read and write accesses to the SDRAM is burst-oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command.

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PC100 and PC133-compliant

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Fully synchronous, all signals registered on positive edge of system clock

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Internal banks for hiding row access/precharge

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Auto precharge, includes concurrent auto precharge and auto refresh modes

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Self refresh modes - Standard and low-power

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LVTTL-compatible inputs and outputs