ISPLSI1016E-125LJN

LATTICE SEMICONDUCTOR  ISPLSI1016E-125LJN  芯片, CMOS ISP EEPLD

The is a high density Programmable Logic Device containing 96 registers, 32 universal I/O pins, four dedicated input pins, three dedicated clock input pins, one Global OE input pin and a Global Routing Pool GRP. The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block GLB. The GLBs are labelled A0, A1...B7. There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.

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High-performance E2CMOS® technology

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In-system programmable

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Offers the ease of use and fast system speed of PLDs