LMK04828BISQE/NOPB

LMK0482xB超低噪音，符合JESD204B时钟抖动清除器与双回路锁相环 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

The is a high-performance Clock Conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade-off between power or performance, dual VCOs, dynamic digital delay, holdover and glitchless analogue delay make the LMK0482x family ideal for providing flexible high performance clocking trees.

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JEDEC JESD204B Support

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Ultra-low RMS jitter

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Up to 14 differential device clocks from PLL2

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Up to 1 buffered VCXO/crystal output from PLL1

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Dual loop PLLatinum™ PLL architecture

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Up to 3 redundant input clocks

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Automatic and manual switch-over modes

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Hitless switching and LOS

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Integrated low-noise crystal oscillator circuit

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Holdover mode when input clocks are lost

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Precision digital delay, dynamically adjustable

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25ps Step analogue delay

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Multi-mode - Dual PLL, single PLL and clock distribution

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Green product and no Sb/Br

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.