CY7C1380D-167AXC

CYPRESS SEMICONDUCTOR  CY7C1380D-167AXC.  芯片, 存储器, SRAM, 18Mb, 并行口 3.4NS TQFP100

The is a 18MB Serial Random Access Memory SRAM integrates 524288 x 36 and 1048576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input. The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable, depth-expansion chip enables, burst control inputs, write enables and global write. Asynchronous inputs include the output enable and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when address strobe processor or address strobe controller are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin. Address, data inputs and write controls are registered on-chip to initiate a self-timed write cycle. Write cycles can be one to 2 or 4 bytes wide as controlled by the byte write control inputs.

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Supports bus operation up to 167MHz

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Registered inputs and outputs for pipelined operation

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3.3V Core power supply

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Fast clock-to-output times - 2.6ns

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Provide high performance 3-1-1-1 access rate

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Separate processor and controller address strobes

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Synchronous self-timed writes

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Asynchronous output enable

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Single cycle chip deselect