SRAM Chip Sync Quad 3.3V 36M-bit 1M x 36 3.1ns 100Pin TQFP T/R
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * JTAG Boundary Scan for BGA package * Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% VVPS: Vdd 1.8V + 5%, Vddq 1.8V + 5% * JEDEC 100-Pin QFP, 119-ball BGA, and 165- ball BGA packages * Lead-free available
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