NXP PUMD3 双极晶体管阵列, BRT, NPN, PNP, 50 V, 200 mW, 100 mA, 30 hFE, SOT-363
集电极-基极反向击穿电压VBRCBO Collector-Base VoltageVCBO| 50V/-50V \---|--- 集电极-发射极反向击穿电压VBRCEO Collector-Emitter VoltageVCEO| 50V/-50V 集电极连续输出电流IC Collector CurrentIC| 100mA/-100mA Q1基极输入电阻R1 Input ResistanceR1| 10KΩ/Ohm Q1基极-发射极输入电阻R2 Base-Emitter ResistanceR2| 10KΩ/Ohm Q1电阻比R1/R2 Q1 Resistance Ratio| 1 Q2基极输入电阻R1 Input ResistanceR1| 10KΩ/Ohm Q2基极-发射极输入电阻R2 Base-Emitter ResistanceR2| 10KΩ/Ohm Q2电阻比R1/R2 Q2 Resistance Ratio| 1 直流电流增益hFE DC Current GainhFE| 30 截止频率fT Transtion FrequencyfT| 耗散功率Pc Power Dissipation| 300mW/0.3W Description & Applications| Features • NPN/PNP resistor-equipped transistors; • Transistors with different polarity and built-in bias resistors R1 and R2 typ. 10 kΩ each • No mutual interference between the transistors • Simplification of circuit design • Reduces number of components and board space APPLICATIONS • Low current peripheral drivers • Replacement of general purpose transistors in digital applications • Control of IC inputs 描述与应用| 特点 •NPN/ PNP电阻配备;晶体管不同极性和内置的偏置电阻R1和R2（典型值10KΩ/Ohm的） •晶体管之间没有相互干扰 •简化电路设计 •减少元件数量和电路板空间 应用 •低电流外设驱动程序 •通用晶体管数字应用的更换 •控制IC投入