CMOS和盖茨 CMOS AND GATES
The is a CMOS triple 3-input AND Gate. This device provides the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.
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60ns Medium-speed operation tPLH, tPHL
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100% Tested for quiescent current at 20V
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1µA Maximum input current
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2.5V at VDD = 15V Noise margin
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Standardized symmetrical output characteristics
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5V, 10V and 15V Parametric ratings
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Meets all requirements of JEDEC tentative standard No.13B
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Green product and no Sb/Br