CDC5801ADBQ

低抖动时钟乘法器和除法器具有可编程延迟 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

The CDC5801A device provides clock multiplication and division from a single-ended reference clock REFCLK to a differential output pair CLKOUT/CLKOUTB. The multiply and divide terminals MULT/DIV0:1 provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference REFCLK ranging from 19 MHz to 125 MHz.

The implemented phase aligner provides the possibility to phase align zero delay between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals.

The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI unit interval. For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.

Depending on the selection of the mode terminals P0:2, the device behaves as a multiplier by 4, 6, or 8 with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals P0:2 user can also bypass the phase aligner and the PLL test mode and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal.

The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.

The CDC5801A device is characterized for operation over free-air temperatures of –40°C to 85°C.