TC7WBL125AFK

TC7WBL125AFK 解码器、多路复用器、信号开关 VFSOP8/US8 标记WLA125

逻辑类型Logic Type| 总线开关 Bus Switch \---|--- 电路数Number of Circuits| 输入数Number of Inputs| 电源电压VccVoltage - Supply| 静态电流IqCurrent - Quiescent Max| 单电源 Single Supply 输出高，低电平电流Current - Output High, Low| 2 V ~ 3.6 V 低逻辑电平Logic Level - Low| The provides two bits of low-voltage, high-speed bus switching. The low ON-resistance of the switch allows connections to be made with minimal propagation delay and while maintaining CMOS low power dissipation. The device comprises dual 2-bit switches with separate bus enable OE signals. When OE is low, the switch is on and port A is connected to port B. When OE is high, the switch is off and a high-impedance state exists between the two ports. All inputs are equipped with protection circuits to guard against static discharge. Operating voltage range: VCC = 2 to 3.6 V High speed: tpd = 0.31 ns max @ 3 V Ultra-low ON-resistance: RON = 5 Ω typ. @ 3 V ESD performance: Machine model ≥ ±200 V Human body model ≥ ±2000 V Power-down protection provided on inputs OE input only Package: US8 高逻辑电平Logic Level - High| TC7WBL125AFK提供2位低电压，高速总线开关。低导通电阻的开关允许以最小的传播延迟连接，同时保持CMOS的低功耗。该器件包括2位开关，双独立总线使能（OE）信号。当OE低，开关打开，端口A连接到端口B。当OE高，开关处于关闭状态，高阻抗状态之间存在着两个端口。所有输入都配有保护电路，以防止静电放电。 工作电压范围：VCC=3.6 V 高速：TPD =0.31NS（最大值）@3 V 超低导通电阻：RON= 5Ω（典型值）@3 V ESD性能：机器型号≥±200 V 人体模式≥±2000 V 掉电保护提供输入（OE输入） 包装：US8 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL| Description & Applications| 描述与应用|