CD54HC4017

具有 10 个解码输出的高速 CMOS 逻辑十进制计数器/除法器

The is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock CP input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count TC output transitions low to high after output ten 9 goes low, and can be used in conjunction with the clock enable CE\\ input to cascade several stages. CE\ disables counting when in the high state. The master reset MR input, when taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.

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2-V to 6-V Operation

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Fully Static Operation

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Buffered Inputs

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Common Reset

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Positive-Edge Clocking

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Balanced Propagation Delay and Transition Times

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V

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Packaged in Ceramic F DIP Package and Also Available in Chip Form H