EVAL-ADF4113EB1

GSM900评估板对于PLL频率合成器 GSM900 Evaluation Board For PLL Frequency Synthesizer

GENERAL DESCRIPTION

The ADF4110 familyoffrequency synthesizers can be used to implement localoscillators inthe upconversion and downcon version sectionsofwireless receivers and transmitters. They

consistofalownoise digitalPFDphasefrequencydetector, a precisionchargepump, a programmablereference divider, programmable A and B counters,and a dual-modulus prescaler

P/P + 1.The A 6-bit and B 13-bit counters,in conjunction withthe dual-modulus prescaler P/P + 1,implement an N dividerN = BP+ A.Inaddition,the 14-bitreference counterR counter allows selectable REFIN frequencies atthe PFD input. A completephase-lockedloopPLL can be implemented ifthe synthesizer is used with an external loopfilter and voltage

controlledoscillator VCO.

FEATURES

ADF4110: 550 MHz; ADF4111:1.2 GHz; ADF4112: 3.0 GHz; ADF4113: 4.0 GHz

2.7 V to 5.5 V power supply

Separate charge pump supply VP allows extended tuning voltage in 3V systems

Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analogand digital lock detect

Hardware and software power-down mode

APPLICATIONS

Base stations for wireless radio GSM, PCS, DCS, CDMA, WCDMA

Wireless handsets GSM, PCS, DCS, CDMA, WCDMA

Wireless LANS

Communications test equipment

CATVequipment