Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 8Pin SOIC
Overview
The W163 products are five-output zero delay buffers. A Phase-Locked Loop PLL is used to take a time-varying signal and provide five copies of that same signal out. The internal feedback to the PLL provides outputs in phase with the reference inputs.
Features
• Spread Aware™—designed to work with SSFTG reference signals
• Outputs may be three-stated
• Available in 8-pin SOIC package
• Extra strength output drive available -15 version
• Internal feedback maximized the number of outputs available in 8-pin package