https://ww1.microchip.com/downloads/en/Appnotes/00799b.pdf
INTRODUCTION
There are many MOSFET technologies and silicon processes in existence today, with new advances being made every day. To make a generalized statement about matching a MOSFET driver to a MOSFET based on r die sizes is very difficult, if not impossible.
As with any design decision, there are multiple variables involved when selecting the proper MOSFET driver for the MOSFET being used in your design. Parameters such as input-to-output propagation delay, quiescent current, latch-up immunity and driver current rating must all be taken into account. Power dissipation of the driver will also effect your packaging decision and driver selection.
Thisdiscusses the details of MOSFET driver power dissipation in relation to MOSFET gate charge and operating frequency. It also discusses how to match MOSFET driver current drive capability and MOSFET gate charge based on desired turn-on and turn-off times of the MOSFET.
Microchip offers many variations of MOSFET drivers in various packages, which allows the designer to select the optimal MOSFET driver for the MOSFET(s) being used in their application.
POWER DISSIPATION IN A MOSFET DRIVER
Charging and discharging the gate of a MOSFET requires the same amount of energy, regardless of how fast or slow (rise and fall of gate voltage) it occurs. Therefore, the current drive capability of the MOSFET driver does not effect the power dissipation in the driver due to the capacitive load of the MOSFET gate.
There are three elements of power dissipation in a MOSFET driver:
1. Power dissipation due to the charging and discharging of the gate capacitance of the MOSFET.
2. Power dissipation due to quiescent current draw of the MOSFET driver
3. Power dissipation due to cross-conduction (shoot-through) current in the MOSFET driver.
As deduced from the equations above, only one of the three elements of power dissipation is due to the charging and discharging of the MOSFET gate capacitance. This portion of the power dissipation is
In order to calculate a value for Equation 1, the gate capacitance of the MOSFET is required. The gate capacitance of a MOSFET is comprised of two capacitances: the gate-to-source capacitance and the gateto-drain capacitance (Miller Capacitance). A common mistake is to use the Input Capacitance rating of the MOSFET (CISS) as the total gate capacitance of the MOSFET. The proper method for determining gate capacitance is to look at the Total Gate Charge (QG) in the MOSFET data sheet. This information is typically shown in the Electrical Characteristics table and as a typical characteristics curve in any MOSFET data sheet.
Table 1 shows a typical example of the data sheet representation of gate charge for a 500V, 14A, N-channel MOSFET. Note that the values given in the data sheet table have conditions associated with them: gate voltage and drain voltage. These conditions effect the gate charge value. Figure 1 shows the gate charge typical characteristic curve for the same MOSFET as it varies with gate voltage and drain voltage. Make sure the gate charge value you use for calculating power dissipation fits the conditions of your application.
Taking a typical value from the graph in Figure 1 for , we get a total gate charge of (VDS = 400V). Using the relationship , we get a gate capacitance value of , which is significantly higher than the input capacitance that is specified in Table 1. This illustrates the fact that when a calculation calls for a gate capacitance value, the total gate capacitance value should be derived from the total gate charge value.
When using maximum values for gate charge from the Electrical Characteristics table for worst-case design, the values must be adjusted for the drain-to-source and gate-to-source voltages in your design.
Using the MOSFET information presented in Table 1 and Figure 1 as an example, the power dissipation in a MOSFET driver due to the charging and discharging of the gate capacitance of this MOSFET with a VGS of , a switching frequency of and a drain-to-souce voltage of would be:
The value for is arrived at by using the graph in Figure 1 and finding the value for at 12V. QG is then by to get the CG value. Knowing that is equal to , the equation for PC could be rewritten as:
A note of importance is that the voltage in this equation is squared. Therefore, a reduction in the gate drive voltage can result in a significant reduction in power loss in the driver. For some MOSFETs, driving the gate voltage above does not result in any further decrease in MOSFET resistance (RDS-ON). Using the same MOSFET as above as an example, a drive results in the following power dissipation:
The reduction in gate voltage (going from 12V to 10V) resulted in a reduction in power dissipation due to gate drive. Further savings will also be seen in the losses due to gate drive voltage reduction.
Equation 3 represents the power dissipation due to MOSFET driver cross-conduction, or what is commonly referred to as shoot-through. This is a result of the P-channel and N-channel FETs in the output drive stage being on at the same time as they transition between the on and off states.
Cross-conduction characteristics are shown in the MOSFET driver data sheet as a typical characteristic curve and as “Crossover Energy vs. Supply Voltage”. An example of this is shown in Figure 2.
The units for the crossover constant are typically shown as . Multiplying this number by the frequency of operation yields a value for average current. Figure 2 illustrates a point that was discussed earlier. Namely, as bias voltage increases, the crossover constant increases and, consequently, the power dissipation in the driver (due to cross-conduction) increases. Therefore, a decrease in driver voltage will result in a decrease in driver power dissipation.
One thing to make note of is that when using a dual driver, the crossover constant is usually shown for both portions of the driver operating. If only one portion of the driver is being used, or the two portions of the driver are operating at different frequencies, be sure to use only half the value for each portion of the driver.
Using the information illustrated in Figure 2 as an example, we will assume it is for a single-output driver operating with a VDD of , at a frequency of . Based on the graph, the crossover constant is found to be .
For this driver, operating at this voltage and frequency, the power dissipation is relatively insignificant. Typically, as the current drive capability of the MOSFET driver increases, the losses due to shoot-through current will also increase. These losses can be significant and need to be taken into account when selecting a package for the MOSFET driver.
Microchip offers surface-mount and pin through-hole packages, ranging from 8-pin MSOPs to 8-pin DFNs to 5-pin TO-220s, allowing for the selection of the package that is most appropriate for your application.
DIE SIZE EFFECT ON GATE CAPACITANCE
As can be expected, the larger the die size of the MOSFET, the larger the effective gate charge. For an illustration of this, browse through any manufacturer's data book. By relating die size to total gate charge, you will find that, as die size increases, the total gate charge will also increase. As advances are made in silicon technology, new MOSFETs are produced that may have the same die size as an older device, but with a lower total gate charge. However, MOSFETs within the same silicon technology still follow the same general rule that as die size goes up, so does the gate charge requirement.
Die sizes will often be referred to in Hex size. Table 2 below gives some typical die sizes and total gate capacitance values for various MOSFET size Hex ratings.
Many suppliers today have also come out with “low gate charge” versions of MOSFETs that allow for faster switching times and lower gate charge losses. These devices allow applications to operate at higher speeds, with lower switching losses in the power MOSFET, as well as lower gate charge losses in the MOSFET driver.
PEAK CURRENT DRIVE REQUIREMENTS
The elements of the MOSFET driver that have been discussed so far have been related to the power dissipation of the MOSFET driver from both internal and external sources.
Matching the MOSFET driver to the MOSFET in the application will primarily be based on the application requires the power MOSFET to be (rise and fall time of the gate voltage). The optimum rise/fall time in any application is based on many requirements, such as EMI (), switching losses, lead/circuit inductance, switching frequency, etc.
The speed at which a MOSFET can be turned on and off is related to how fast the gate capacitance of the MOSFET can be charged and discharged. The relationship between gate capacitance, turn-on/turn-off time and the MOSFET driver current rating can be written as:
Knowing the relationship given earlier for gate charge is:
The above equation can be rewritten as:
The relationship shown in the equations above assumes that a constant current source is being used for the current (I). By using the peak drive current of the MOSFET driver, some error will be incurred.
MOSFET drivers are rated by the driver output peak current drive capability. This peak current drive capability is generally given for one of two conditions. Either the MOSFET or the MOSFET driver output is (usually , as this is the gate threshold voltage at which the MOSFET begins to turn on and the comes into play). The peak current rating is also generally stated for the maximum bias voltage of the part. This means that if the MOSFET driver is being used with a lower bias voltage, the peak current drive capability of the MOSFET driver will be lower.
Design Example:
Using the following design parameters, the MOSFET driver peak output current rating will be found:
MOSFET gate charge = 20 nC (Q)
MOSFET gate voltage = 12V (dV)
Turn-on/turn-off time = 40 ns (dT)
The equation has produced a peak drive current requirement of 0.5A. However, the gate drive voltage in the design parameters is 12V, and this must be taken into account when selecting the appropriate driver. For instance, if the driver you are selecting is rated for 0.5A at 18V, the peak output current at 12V will be less than 0.5A. For this reason, a driver with a output current at would be chosen for this particular application.
Any external resistance between the MOSFET driver output and the gate of the power MOSFET will also need to be taken into account, as this will reduce the peak charging current supplied to the gate capacitance. This drive configuration is shown in Figure 4.
TYPICAL MOSFET DRIVER GATE DRIVE CONFIGURATIONS
There are many circuit configurations that MOSFET drivers can be used in. Often times, due to the high peak currents, fast rise/fall times of the drive voltages and inductance in long board traces, additional clamp circuitry is required. Figures 3 through 6 show typical gate drive circuit configurations that are often used.
The most ideal MOSFET driver circuit is shown in Figure 3. This configuration is often used in boost, flyback and single switch forward power supply switching topologies. With proper layout techniques and appropriate bias voltage bypass capacitors, very good rise and fall times of the MOSFET gate voltage can be achieved. In addition to having local bypass capacitance on the bias voltage, the grounding of the MOSFET driver is also important.
In many gate drive applications, it may be necessary to limit the peak gate drive current in order to slow down the rise of the gate voltage. This is usually done to lower the EMI noise generated by fast slew rates of the MOSFET drain voltage. Slowing the rise and fall time of the MOSFET gate voltage can be accomplished by either changing to a MOSFET driver that has a lower peak current rating or by adding a series gate drive resistor, as shown in Figure 4.
In applications where the MOSFET driver is not placed close to the MOSFET it is driving, there will be inductance between the output of the driver and the gate of the MOSFET. This can result in the gate voltage of the MOSFET ringing above VDD and below ground. If the peak voltage exceeds the maximum-rated gate voltage of the MOSFET, the MOSFET can be damaged and, thus, lead to failure. This voltage can be clamped by adding a zener diode from the gate to the source of the MOSFET, as is shown in Figure 5. When possible, the board trace length between the MOSFET driver and the MOSFET should be made as short as possible to limit this inductive ringing effect. Inductance between the driver output and gate of the MOSFET can also effect the MOSFET driver’s ability to hold the gate of the MOSFET low during a transient condition.
Figure 6 shows two different gate drive configurations using gate drive transformers. Gate drive transformers can be used in both high- and low-voltage applications where an isolation boundary between the control circuitry and the power MOSFET is needed for either safety regulations or for a situation in which a high-side floating gate drive is required.
Circuits A and B in Figure 6 show a gate drive transformer being used in a single-switch forward application. The resistor and capacitor that are in series with the MOSFET driver output and gate drive transformer are used to balance the volt-time of the gate drive transformer. Because the volt-time of the gate drive transformer must be balanced (as is the case with any transformer), a negative gate-to-source voltage is also applied to the gate of the power MOSFET during the off time of the switching cycle. This can often cause switching time delays at turn-on. If this is an undesired effect, the circuit configuration in B can be used. This circuit uses the negative gate drive voltage to turn on the additional small-signal FET that shorts the gate-tosource node of the main power MOSFET in order to turn it off and keep the gate voltage at 0V. The drive configurations shown in A and B can be used for a two-switch forward topology as well.
MICROCHIP MOSFET DRIVER FAMILIES
Microchip offers several MOSFET driver families. These are:
The was the world’s first CMOS MOSFET driver. It was a dual-output device capable of up to 1.5A peak currents at 18V. This 1.5A driver also came in two other versions, the dual non-inverting TC427 driver and one inverting plus one non-inverting in the TC428 driver.
The family is the second generation of the TC426 family that, through improved processing and design, has less propagation delay and draws half the power of the first generation. These improvements have been incorporated into all drivers with four numeric digits in the part number.
Another important improvement in the second-generation families is their ability to have the input signal operate below the negative rail (ground) by as much as 5V. This parameter is very useful in systems where the control circuit ground is not closely tied to the power or source ground of the MOSFET. These two grounds often move relative to one another.
The family of drivers incorporates all of the improvements of the TC4426 family, in addition to having matched propagational delay times. With matched propagational delay times and matched rise and fall times, this family of drivers is an ideal choice when duty cycle integrity is important.
Thefamily is a special, low-cost version of the TC426\27\28 family that does not have the below-rail protection on the input. It is a good choice for large-volume OEMs.
Following the same part numbering pattern as the 1.5A TC426\27\28 family, the family of dual drivers has a 3A output capacity. The TC4424 is a dual non-inverting driver and the TC4425 is one inverting plus one non-inverting driver.
The is a single inverting driver (like its predecessor the TC429), while the TC4420 is non-inverting. This family has a 6A drive capability at 18V. The TC4429 can slew a 10,000 pF load at 18V in 65 nsec, typically.
The () and () are a family of 9A, single-output MOSFET drivers that are pin-compatible with the TC4420/29 6A MOSFET drivers. This provides a nice migration path for those applications that may need more gate drive current capability than the 6A family can deliver. The TC1410(N), TC1411(N), TC1412(N), TC1413(N), TC4420/29 and TC4421/22 are all single-output drivers that are pin-compatible with each other.
Table 3 on the following page shows the performance of the various drivers under production test methods. The characteristics of those drivers are detailed in their individual data sheets. This table is intended only as a guide for comparing specifications.
The following families of power drivers are made with a CMOS process to interface between low-level control functions and high-power switching devices, particularly power MOSFETs. The devices are also an optimum choice for capacitive drivers where 1.2A thru 9A may be switched. Both inverting and non-inverting outputs are available, as well as dual-input logic gates. Microchip offers additional MOSFET drivers that are not listed in Table 3. For a complete listing of Microchip's 38 MOSFET driver product offerings, please visit our web site at www.microchip.com.
CONCLUSION
There are many parameters to consider when matching the appropriate MOSFET driver to the MOSFET in your application. However, . Table 3 is intended to be used as a general guide to help in narrowing-down the search.
As with any electronic device, no one device is appropriate for every application, which is why Microchip Technology supplies a variety of MOSFET driver current ratings, output drive polarities and input logic configurations.
BUK7Y3R0-40H
Parametrics
| Type number | Package version | Package name | Product status | Channel type | Nr of transistors | VDS [max] (V) | RDSon [max] @ VGS = 10 V (mΩ) | Tj [max] (°C) | ID [max] (A) | QGD [typ] (nC) | QG(tot) [typ] @ VGS = 10 V (nC) | Ptot [max] (W) | Qr [typ] (nC) | VGSth [typ] (V) | Automotive qualified | Ciss [typ] (pF) | Coss [typ] (pF) | Date |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BUK7Y3R0-40H | SOT669 | LFPAK56; Power-SO8 | Production | N | 1 | 40 | 3 | 175 | 120 | 6.3 | 34 | 172 | 19.5 | 3 | Y | 2417 | 688 | 2017-07-04 |
BUK7Y3R0-40H
https://www.nexperia.com/products/mosfets/automotive-mosfets/BUK7Y3R0-40H.html
Automotive qualified N-channel MOSFET using the latest Trench 9 low ohmic superjunction technology, housed in a robust LFPAK56 package. This product has been fully designed and qualified to meet AEC-Q101 requirements delivering high performance and endurance.
[1] 120A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature.
[2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[3] Refer to application note AN10273 for further information.
10. Characteristics
typical and maximum value of the capacitance between terminals, with drain-source terminals short-circuited for alternating voltage, of a field-effect transistor
: typical and maximum value of the capacitance between terminals, with gate-source terminals short-circuited for alternating voltage, of a field-effect transistor
What are MOSFETs? - MOSFET Parasitic Capacitance and Its Temperature Characteristic
What are MOSFETs? - MOSFET Parasitic Capacitance and Its Temperature Characteristic
In continuation of the previous discussion of Si transistor types, features and basic characteristics, we here provide an additional explanation of the characteristics of Si MOSFETs that are at present widely used as power switches.
Due to their structure, MOSFETs have a parasitic capacitance, as indicated in the diagram below. The diagram below is for an example of an N-channel MOSFET, but the situation is much the same for P-channel devices. In the power MOSFETs we are here considering that handle large amounts of power, the parasitic capacitance must be regarded as a parameter that limits the usage frequency and switching speed.
The drain and source of a MOSFET are insulated from the gate by the gate oxide film. A PN junction is formed between the drain and source with substrate intervening, and a parasitic ("body") diode is present.
The gate-source capacitance Cgs and gate-drain capacitance Cgd in the diagram below are determined by the capacitance of the gate oxide film. The drain-source capacitance Cds is the junction capacitance of the parasitic diode.
The three parameters Ciss, Coss, Crss appearing on MOSFET data sheets in general relate to these parasitic capacitances. On data sheets which provide separate descriptions of static characteristics and dynamic characteristics, these are classified as dynamic characteristics. These are important parameters affecting switching performance.
Ciss is the input capacitance, and is the capacitance obtained by totaling the gate-source capacitance Cgs and the gate-drain capacitance Cgd; it is the capacitance of the MOSFET as a whole, as seen from the input. This capacitance must be driven (charged) in order to cause the MOSFET to operate, and so is a parameter of importance when studying the drivability of an input device or input losses. Qg is the amount of charge necessary to drive (charge) Ciss.
Coss is the output capacitance, obtained by adding the drain-source capacitance Cds and the gate-drain capacitance Cgs, and is the total capacitance on the output side. If Coss is large, a current arising due to Coss flows at the output even when the gate is turned off, and time is required for the output to turn off completely.
Crss is the gate-drain capacitance Cgd itself, and is called the feedback capacitance or the reverse transfer capacitance. If Crss is large, the rise in drain current is delayed even after the gate is turned on, and the fall in current is delayed after the gate is turned off. In other words, this parameter greatly affects switching speed. Qgd is the charge amount necessary to drive (charge) Crss.
These capacitances exhibit a dependence on the drain-source voltage VDS. As indicated in the graph, there is a tendency for capacitance values to be reduced as VDS is increased.
Ciss, Coss and Crss change hardly at all with temperature. Hence it can be said that switching characteristics are hardly affected at all by temperature changes. Actual measurement examples are shown below.
Here we have explained parasitic capacitances, which are dynamic characteristics of MOSFETs. Next time, we will discuss device switching.
MOSFET Gate Drive Circuit
application_note_en_20180726_AKX00068.pdf
https://toshiba.semicon-storage.com/info/docget.jsp?did=59460
1. Driving a MOSFET
1.1. Gate drive vs. base drive
Whereas the conventional bipolar transistor is a , the MOSFET is a .
Figure 1.1 illustrates a bipolar transistor. A current must be applied between the base and emitter terminals to produce a flow of current in the collector. Figure 1.2 shows a MOSFET, which produces a flow of current in the drain when a voltage is applied between the gate and source terminals.
The gate of a MOSFET is composed of a silicon oxide layer. Since the gate is insulated from the source, an application of a DC voltage to the gate terminal does not theoretically cause a current to flow in the gate, except in transient periods during which the gate is charged and discharged. In practice, the gate has a tiny current on the order of a few nanoamperes. When there is no voltage between the gate and source terminals, no current flows in the drain except leakage current, because of a very high drain-source impedance.
1.2. MOSFET characteristics
MOSFETs have the following characteristics:
- · Since the MOSFET is a voltage-driven device, no DC current flows into the gate.
- · In order to turn on a MOSFET, a voltage higher than the rated gate threshold voltage Vth must be applied to the gate.
- ·While in a steady on or off state, the MOSFET gate drive basically consumes no power.
- · The gate-source capacitance of a MOSFET seen by the driver output varies with its internal state.
MOSFETs are often used as switching devices at frequencies ranging from several kHz to more than several hundreds of kHz. The low power consumption needed for gate drive is an advantage of a MOSFET as a switching device. MOSFETs designed for low-voltage drive are also available.
The gate of a MOSFET can be considered to be a capacitance. Figure 1.3 shows different capacitances in a MOSFET. The gate voltage of a MOSFET does not increase unless its gate input capacitance is charged, and the MOSFET does not turn on until its gate voltage reaches the gate threshold voltage Vth. The gate threshold voltage Vth of a MOSFET is defined as the minimum gate bias required for creating a conduction channel between its source and drain regions.
In considering a drive circuit and a drive current, the gate charge Qg of a MOSFET is more important than its capacitances. Figure 1.4 illustrates the definitions of parameters regarding the gate charge necessary to raise the gate voltage.
During the turn-on of a MOSFET, a current flows to its gate, charging the gate-source and gate-drain capacitances. Figure 1.5 shows a test circuit for gate charge. Figure 1.6 shows the gate-source voltage curve over time obtained when a constant current is applied to the gate terminal. Since the gate current is constant, the time axis can be expressed in terms of gate charge Qg by multiplying time by constant gate current IG. (The gate charge is calculated as Qg=IG×t.)
The gate of a MOSFET starts accumulating electric charge when a voltage is applied to it. shows a gate charge circuit and a gate charge waveform. When a MOSFET is connected to an inductive load, it affects the reverse recovery current of the diode in parallel to the MOSFET as well as the MOSFET gate voltage. This explanation is omitted here.
- ① During the period t0 to t1, the gate drive circuit charges the gate-source capacitance Cgs and the gate-drain capacitance Cgd via the gate series resistor R until the gate voltage reaches its threshold Vth. Since Cgs and Cgd are charged in parallel, the following equation is satisfied. The gate voltage VGS is calculated as:
- ②During the period t1 to t2, VGS exceeds Vth, causing a current to flow in the drain, which eventually becomes the main current. Cgs and Cg continue to be charged in this period. As the gate voltage increases, the drain current increases. At t2, the gate voltage reaches the Miller voltage, VGS(pl). t2 can be calculated by substituting VGS(pl) for VGS(t2) in Equation (1). As in the period t0 to t1, the delay time t2 is proportional to R(Cgs+Cgd).
- During the period t2 to t3, VGS remains constant at the VGS(pl) voltage (due to the Miller effect). The gate voltage remains constant. As the entire main gate current keeps flowing through the MOSFET, the drain voltage reaches its turn-on voltage, (RDS(on)×ID) at t3. Since the gate voltage remains constant during this period, the drive current flows to Cgd, not to Cgs. The charge accumulated in Cgd (Qgd) during this period equals the product of a current flowing to the gate circuit and the voltage fall time (t3–t2):
- During the period t3 to t4, the gate is charged to the oversaturated state. Both Cgs and Cgd are charged until the gate voltage (VGS) reaches the gate supply voltage. Since the turn-on transient has already disappeared, the MOSFET suffers no switching loss during this period.
1.3. Gate drive power
The power consumed by the MOSFET gate drive circuit increases in proportion to its frequency. This section describes the power consumption by the gate drive circuit shown in Figure 1.8.
In Figure 1.8, a gate pulse voltage VG is applied between the gate and source terminals of a MOSFET via a gate resistor R1. Suppose that VGS rises from 0 V to VG (10 V in Figure 1.9). VG is sufficiently high to turn on the MOSFET. The MOSFET is initially off and turns on as VGS changes from 0 V to VG. The gate current flowing during this transient switching period is calculated as:
The energy supplied from the drive power supply minus the energy accumulated in the gate is consumed by the gate resistor.
During the turn-off period, the energy accumulated in the gate is consumed by the gate resistor.
The energy E consumed per switching event is equal to the amount of energy supplied by the drive circuit. The average power consumption of the gate drive circuit PG can be calculated by multiplying E by the switching frequency fsw:
2. Example of a MOSFET gate drive circuit
The basic requirements for a MOSFET drive circuit include an ability to apply a voltage sufficiently higher than Vth to the gate and a drive capability to sufficiently charge the input capacitance. This section describes an example of a drive circuit for an N-channel MOSFET.
Figure 2.1 shows a basic MOSFET drive circuit. In practice, the capacitance of a MOSFET to be driven and its usage conditions must be considered in designing a drive circuit.
2.2. Logic drive
There is a growing need for MOSFETs for switching applications (load switches) to provide a conducting path in a circuit only when it is operated, and thereby reduce the power consumption of electronic devices. At present, MOSFETs are directly driven by a logic circuit or a microcontroller in many applications.
Figure 2.2 shows an example of a circuit for turning on and off a power relay. Since turn-on and turn-off times may be as slow as a few seconds for load switches, the MOSFET gate can be driven with a small current.
2.3. Drive voltage conversion
(1) Conversion of a drive voltage to 15 V
Figure 2.3 shows an example of driving a MOSFET with a digital logic. This circuit boosts a drive voltage when the MOSFET cannot be driven at 5 V. R2 connected in series with the gate resistor R3 increases the gate drive resistance, making it difficult to drive the MOSFET in saturation mode. This slows the switching speed of the MOSFET and therefore increases the switching loss. On the contrary, reducing R2 causes a large drain current ID to flow to the drive circuit during the turn-off period of the MOSFET, increasing the power consumption of the drive circuit.
(2) Push-pull circuit
The drawback of the circuit shown in Figure 2.3 is that boosting a drive voltage from digital logic increases the power consumption of the drive circuit. This problem can be solved by adding a push-pull circuit as shown in Figure 2.4.
A push-pull circuit is also used when a drive current for a MOSFET is insufficient.
2.4. High-side drive from a half or full bridge
Figure 2.5 shows how to use MOSFETs in a half- or full-bridge configuration. To turn on the N-channel MOSFET on the high side Q1, a higher voltage against source terminal must be applied to its gate terminal.
Since the source voltage of Q1 varies with the turn-on and turn-off of the low-side MOSFET Q2, Q1 and Q2 cannot share the same ground line of the drive power supply.
Figure 2.5 shows an example of a circuit that drives a high-side device using a high-voltage device and a bootstrap circuit. The switching frequency is limited, depending on the output capacitance and the loss of a level shifter.
2.4.2. Pulse transformer drive (insulated switching)
The use of a pulse transformer eliminates the need for a separate drive power supply. It has a drawback, however, in terms of the power consumption of a drive circuit. A pulse transformer is sometimes used to isolate a MOSFET from its driver in order to protect the drive circuit from the MOSFET’s trouble.
Figure 2.6 shows an example of a simple circuit. The purpose of the Zener diode in this circuit is to quickly reset the pulse transformer. The circuit shown in Figure 2.7 has an additional PNP transistor to improve the switching performance.
The circuit shown in Figure 2.8 has a capacitor in series with a pulse transformer in order to apply a reverse bias to a MOSFET during its turn-off period and thereby improve the switching speed. Since the capacitor blocks the DC bias, it also prevents the pulse transformer from reaching a saturation point.
2.4.3. Using a photocoupler and a floating power supply
An optically isolated device (photocoupler) is also used for MOSFET gate drive. A separate power supply is necessary for the photocoupler output. To use a photocoupler to drive the high side of a half or full bridge, a floating power supply is necessary. Care should be exercised as to the speed and drive capability of the photocoupler. Photocouplers specifically designed for MOSFET/IGBT gate drive are available from Toshiba.
3. Power supply for the MOSFET drive circuit
3.1. Transformer-isolated power supply
When both the upper and lower arms of an H-bridge, a three-phase inverter or a similar circuit are used to drive MOSFETs, the power supplies for the upper and lower arms must be isolated from each other.
Figure 3.1 shows an example of power supplies using a transformer.
The MOSFETs driven by the lower arm can share the same power supply. Therefore, an H-bridge needs three power supplies whereas a three-phase bridge needs four.
3.2. Bootstrap circuit
A bootstrap circuit, which consists of diodes and capacitors, can be used in place of a floating power supply. When MOSFETs are driven by both the upper and lower arms of an inverter or a similar circuit, the bootstrap capacitor C can be used in each phase as shown in Figure 3.2 instead of a floating power supply. Initially, the devices in the lower arm must be turned on to charge capacitor C from the lower-arm power supply through the path highlighted by a dashed line. The capacitor C is charged through this path each time the MOSFET of the lower arm turns on. Since the on-duty cycle of the upper-arm devices has a certain relationship with the amount of charge stored on the capacitor C, there is a limit to the on-duty cycle of the upper arm. As is the case with the output voltage, fluctuations of the gate voltage of the upper arm make it sensitive to noise. Therefore, care should be exercised in designing the upper-arm gate circuit.
3.3. Charge pump
A charge pump consists of an oscillation circuit, diodes and capacitors. Each stage of a charge pump boosts the voltage stored in the capacitor. The charge pump shown in Figure 3.3 can be used to drive the high side when MOSFETs are driven by both the upper and lower arms. Unlike a bootstrap circuit, the charge pump does not impose any limit to the duty cycle of the output device.
4. Considerations for the MOSFET drive circuit
4.1. Considerations for the gate voltage VGS conditions
VGS is important for MOSFET gate drive.
The on-state resistance of MOSFETs is low when they operate in the linear region (i.e., at a voltage lower than pinch-off voltage).
Therefore, for switching applications, you can reduce the on-state resistance by using MOSFETs in the low VDS region.
· A MOSFET turns on when its gate voltage VGS exceeds its threshold voltage Vth as shown in Figure 4.2. Therefore, VGS must be sufficiently higher than Vth.
· The higher the VGS, the lower the RDS(ON) value tends to become.
· The higher the temperature, the higher the RDS(ON) value becomes (Figure 4.3).
· In order to reduce loss, it is important to increase VGS in order to minimize the resistance of the device at the current level at which it is used (Figure 4.4). Conversely, a high VGS value increases the ratio of drive loss to the total loss for high-frequency switching.
Selecting the optimal MOSFET and gate drive voltage is therefore critical. For many of Toshiba’s power MOSFETs, it is generally recommended to drive their gates at a VGS of 10 V. Toshiba's product portfolio also includes power MOSFETs designed for gate drive at a VGS of 4.5 V. Select the power MOSFET that best suits your system requirements.
4.2. Gate voltage, peak current and drive loss
In designing a drive circuit for a MOSFET, a drive loss and a current for charging the gate input capacitance are very important as described in Section 1.3, “Gate drive power.”
Increasing the gate voltage reduces RDS(ON) and therefore the steady-state loss. However, since Q=CV, increasing the gate voltage increases Qg and therefore the gate current and the drive loss. When MOSFETs switch at a high frequency in light-load applications, the gate drive losses significantly affect their total loss. Care should be exercised in designing a drive circuit.
4.3. Gate resistors and switching characteristics
Generally, a resistor is connected to the gate terminal of a MOSFET. The purposes of the gate resistor include suppression of inrush current and a reduction in output ringing. A large gate resistor decreases the switching speed of a MOSFET. This results in an increase in power loss, a reduction in performance and potential heat issues. Conversely, a small gate resistor increases the switching speed of a MOSFET, which makes it susceptible to voltage surge and oscillation and therefore to device failure and damage. It is therefore important to optimize the MOSFET switching speed by adjusting the gate resistor value.
We considered the switching waveform of a MOSFET for the circuit shown in Figure 4.5 using simulation. In order to estimate an actual circuit, a wire stray inductance was inserted in the simulation circuit. The magnitude and period of output ringing depend on stray inductance.
We simulated to obtain the switching-off waveforms of the circuit shown in Figure 4.5, changing the gate resistor R3 to 1, 10 and 50. Figure 4.6 shows the simulation results. As described above, reducing the gate resistor value increases the switching speed of a MOSFET at the expense of an increase in the ringing voltage. Conversely, increasing the gate resistor value reduces the ringing voltage, but reduces the switching speed of a MOSFET and therefore increases its switching loss. This is because the gate resistor value and the gate voltage restrict the gate charge current of a MOSFET.
4.4. 栅极驱动的注意事项
在 MOSFET 的栅极和源极之间添加一个外部齐纳二极管，可以有效防止发生静电放电和栅极尖峰电 压。但要注意，齐纳二极管的电容可能有轻微的不良影响。
如第 4.3 节“栅极电阻器和开关特性”中所述，开关速度根据栅极电阻器值而有所不同。增大栅极电 阻器值会降低MOSFET的开关速度，并增大其开关损耗。减小栅极电阻器值会增大MOSFET的开关速度， 但由于线路杂散电感和其它因素的影响，可能在其漏极端子和源极端子之间产生了尖峰电压。 因此，必须选择最佳的栅极电阻器。有时会使用不同的栅极电阻器来开通和关断 MOSFET。图 4.8 显示了使用不同的栅极电阻器进行开通和关断的示例。
MOSFET 的一大问题在于其漏栅电容会导致出现寄生开通（自开通）现象。关断后，MOSFET 的源 极和漏极之间形成陡峭的 dv／dt。产生的电流经由漏栅电容流到栅极。导致栅极电阻器中发生的电压降提 高栅极电压。该电流计算如下：
iDG＝Cgd·dVDS／dt
图 4.9 显示了电流通路。 如果 dv／dt 的斜率极为陡峭，则根据栅源电容与栅漏电容的比率为 MOSFET 的栅极施加电压。如果 出现这种情况，可能会发生自开通。
如果 dv／dt 的斜率极为陡峭，则根据栅源电容与栅漏电容的比率为 MOSFET 的栅极施加电压。如果 出现这种情况，可能会发生自开通。 如果在二极管反向恢复期间对处于关断状态的 MOSFET 施加快速变化的电压，也可能发生自开通。 有三种方法可以防止出现自开通现象：
（1） 在栅极和源极之间添加一个电容器 在栅极和源极之间插入的电容器会吸收因 dv／dt 产生的漏栅电流。该电路如图 4.10 中所示。由于栅 源电容器与 Cgs 在 MOSFET 内部并联连接，因此栅极电荷会增加。如果栅极电压固定，您可以通过改变 栅极电阻器值来保持 MOSFET 的开关速度不变，但这样会增大消耗的驱动功率。
（2） 米勒箝位电路 米勒箝位电路利用开关器件使 MOSFET 的栅极与源极之间的通路发生短路。通过在相关 MOSFET 的栅极和源极之间添加另一个 MOSFET 来实现短路。在图 4.11 中，如果电压降至预定义电压以下，低于 米勒电压，则通过比较器提供逻辑高，开通栅极和源极之间的 MOSFET。而这样又会使输出 MOSFET 的 栅源通路发生短路，并抑制通过反馈电容器 Crss 和栅极电阻器的电流导致的栅极电压升高。
（3） 可将关断栅极电压驱动到负值，避免其超过 Vth。但这种方法需要负电源。
我们使用图 4.12 中所示的电路模拟自开通现象。自开通由 iDG（dv／dt 电流）和栅极电阻造成，会导 致发生误开通。 在反向恢复模式中，如果 Q2 在电感负载电流通过 Q1 的二极管回流时开通，电感电流会流过 Q2，导 致相关的二极管关断。我们研究了对关断状态的 MOSFET 施加高 dv／dt 电压时会发生的情况。为促使发 生自开通现象，图 4.12 中只改变了与 Q1 相关的栅极电阻器 R4。
图 4.13 显示了无自开通现象的波形，图 4.14 显示了有自开通现象的波形。
接下来，如图 4.15 中所示，我们为图 4.12 中所示电路在 MOSFET Q1 的栅极端子和源极端子之间添 加了一个电容器。该电容器的用途是吸收栅电流（Cgd·dVDS／dt），以便降低栅极电阻器产生的栅极电 压，从而降低自开通电压。
图 4.16 显示了改进后的波形。由于栅源电容器的添加改变了 MOSFET 开关时间，应一并调整其电容 和栅极电阻。
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https://www.infineon.com/dgdl/Infineon-Effects_of_a_SiC_TMOSFET_tractions_inverters_on_the_electric_vehicle_drivetrain-Editorials-v01_00-EN.pdf?fileId=5546d4627600a6bc017601596e5162b8