1 features ?low-voltage and standard-voltage operation –2.7 (vcc = 2.7v to 5.5v) –1.8 (vcc = 1.8v to 3.6v) ?internally organized 16,384 x 8 and 32,768 x 8 ?2-wire serial interface ?schmitt trigger, filtered inputs for noise suppression ?bidirectional data transfer protocol ?1 mhz (5v), 400 khz (2.7v, 2.5v) and 100 khz (1.8v) compatibility ?write protect pin for hardware and software data protection ?64-byte page write mode (partial page writes allowed) ?self-timed write cycle (5 ms typical) ?high reliability –endurance: one million write cycles –data retention: 40 years ?automotive grade, extended temperature and lead-free devices available ? 8-lead jedec pdip, 8-lead jedec and eiaj soic, 8-lead map, 8-lead tssop and 8-ball dbga2tm packages description the at24c128/256 provides 1、特点·低压和标准电压操作-2.7(VCC=2.7v至5.5v)-1.8(VCC=1.8v至3.6v)·内部组织16,384x8和32,768x8·2线串行接口·过滤器输入噪声抑制·双向数据传输协议·1MHz(5v)、400kHz(2.7v、2.5v)和100kHz（1。兼容·硬件和软件数据保护引脚·64字节页面写入模式(允许部分页面写入)·自动定时写入周期(5ms典型)·高可靠性-持久性:100万个写入周期-数据保留:40年·可用于汽车等级、扩展温度和无铅设备·8引线JedecPDIP，8引线Jedec和eiajSoic，8引线地图，8引线TSSOP和8球dbga2tm包描述at24c128/256提供
3 at24c128/256 0670k–seepr–7/03 pin description serial clock (scl): the scl input is used to positive edge clock data into eacheeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collectordevices. 3、at24c128/2560670k-seepr-7/03引脚描述串行时钟(SCL)：SCL输入正边时钟数据Eacheeprom从每个设备中输出负边缘时钟数据。 串行数据(SDA)：SDA串行数据传输采用双向引脚。 引脚由开路漏驱动，线芯可采用任何数量的其他开路漏或开路收集设备。
device/page addresses (a1, a0): the a1 and a0 pins are device address inputs thatare hardwired or left not connected for hardware compatibility with at24c32/64. when thepins are hardwired, as many as four 128k/256k devices may be addressed on a single bussystem (device addressing is discussed in detail under the device addressing section). whenthe pins are not hardwired, the default a1 and a0 are zero. 设备/页面地址(A1，A0)：A1和A0引脚是设备地址输入，它们是硬连接，或没有连接AT24C32/64硬件兼容。 当引脚是硬连线时，多达4个128k/256k可在单个总线系统上找到设备(在设备找址部分详细讨论)。 当引脚不是硬连线时，默认情况下A1和A0为零。
write protect (wp): the write protect input, when tied to gnd, allows normal write oper-ations. when wp is tied high to vcc, all write operations to the memory are inhibited. if leftunconnected, wp is internally pulled down to gnd. switching wp to vcc prior to a write oper-ation creates a software write protect function. 写保护(WP)：写保护输入，绑定到GND允许正常的写作操作。 当wp与vcc高度绑定时，所有内存的写入操作都会受到抑制。 若左连接，wp将内部拉到GND。 在写作之前WP切换到VCC会创建软件写保护功能。
memory organization at24c128/256, 128k/256k serial eeprom: the 128k/256k is internally organized as256/512 pages of 64-bytes each. random word addressing requires a 14/15-bit data wordaddress. 内存组织在24c128/256，128k/256k串行EEPROM：128k/256k64字节内部组织为256/512页。 随机字搜索需要14/15位数据字地址。
device operation clock and data transitions: the sda pin is normally pulled high with an externaldevice. data on the sda pin may change only during scl low time periods (refer to datavalidity timing diagram). data changes during scl high periods will indicate a start or stopcondition as defined below. 操作时钟和数据转换：SDA外部设备通常部设备抬高。 只有在SCL低时间段(见数据值定时图)，SDA只有引脚上的数据才能改变)。 在SCL高周期数据变更将指示下面定义的开始或停止条件。
start condition: a high-to-low transition of sda with scl high is a start condition whichmust precede any other command (refer to start and stop definition timing diagram).stop condition: a low-to-high transition of sda with scl high is a stop condition. after aread sequence, the stop command will place the eeprom in a standby power mode (refer tostart and stop definition timing diagram). 启动条件：SDA与SCL高到低的过渡是启动条件，必须先于任何其他命令(见启动和停止定义时序图)。停止条件:SDA与SCL高、低、高的过渡是停止条件。 在AREAD序列后，将停止命令EEPROM将其放置在备用电源模式下(请参考启停定时图)。
acknowledge: all addresses and data words are serially transmitted to and from theeeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowl-edge that it has received each word. 承认：所有地址和数据单词都以8位单词连续传输到他们的毕业舞会上。第九个时钟周期，EO舞会发送零来承认它已经收到了每个单词。
standby mode: the at24c128/256 features a low power standby mode which is enabled:a) upon power-up and b) after the receipt of the stop bit and the completion of any internaloperations. 待机模式：at24c128/256具有低功耗待机模式，启用：a)启动和完成任何内部操作b)在收到停止位并完成任何内部操作后。
memory reset: after an interruption in protocol, power loss or system reset, any 2-wirepart can be reset by following these steps: (a) clock up to 9 cycls, (b) look for sda high ineach cycle while scl is high and then © create a start condition as sda is high. 内存重置：在协议中断、电源丢失或系统重置后，任何二线部分都可以通过以下步骤进行重置： (A)时钟最多9个周期， (B)在SCL高的情况下寻找SDA高周期 ©创建SDA高的启动条件。
device addressing the 128k/256k eeprom requires an 8-bit device address word following a start condition toenable the chip for a read or write operation (refer to figure 1). the device address word con-sists of a mandatory one, zero sequence for the first five most significant bits as shown. this iscommon to all 2-wire eeprom devices. 寻址128k/256k EEPROM的设备需要一个8位设备地址字，它遵循启动条件，使芯片能够进行读或写操作（参见图1）。 设备地址字con-sist的一个强制性的，零序列的前五个最重要的比特，如图所示。 这是常见的所有二线EEPROM设备。
the 128k/256k uses the two device address bits a1, a0 to allow as many as four devices onthe same bus. these bits must compare to their corresponding hardwired input pins. the a1and a0 pins use an internal proprietary circuit that biases them to a logic low condition if thepins are allowed to float. 128k/256k使用两个设备地址位A1，A0，允许在同一总线上有多达四个设备。 这些位必须与它们相应的硬连线输入引脚进行比较。 如果允许引脚浮动，则A1和A0引脚使用内部专有电路，将它们偏置到逻辑低条件。
the eighth bit of the device address is the read/write operation select bit. a read operation isinitiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is notmade, the device will return to a standby state. 设备地址的第八位是读/写操作选择位。 如果此位高，则启动读操作，如果此位低，则启动写操作。 在比较设备地址时，EEPROM将输出零。 如果没有进行比较，设备将返回待机状态。
data security: the at24c128/256 has a hardware data protection scheme that allows theuser to write protect the whole memory when the wp pin is at vcc. 数据安全：at24c128/256具有硬件数据保护方案，允许用户在WP引脚位于VCC时写入保护整个内存。
write operations byte write: a write operation requires two 8-bit data word addresses following the deviceaddress word and acknowledgment. upon receipt of this address, the eeprom will againrespond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bitdata word, the eeprom will output a zero. the addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. at this time the eeprom entersan internally-timed write cycle, twr, to the nonvolatile memory. all inputs are disabled duringthis write cycle and the eeprom will not respond until the write is complete (refer to figure 2). 写操作字节写：写操作需要在设计地址单词和确认之后两个8位数据单词地址。收到此地址后，电子舞会将以零响应，然后在第一个8位数据字中同时响应时钟。收到8位数据字后，EEPI将输出为0。寻址设备，如微控制器，必须以停止条件终止写序列。在这个时候，电子舞会的娱乐内部时间写作周期，TVR，到非挥发性记忆。所有输入都在这个写周期中被禁用，并且EO舞会在写完成之前不会响应（参考图2）。
page write: the 128k/256k eeprom is capable of 64-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send astop condition after the first data word is clocked in. instead, after the eeprom acknowledgesreceipt of the first data word, the microcontroller can transmit up to 63 more data words. theeeprom will respond with a zero after each data word received. the microcontroller must ter-minate the page write sequence with a stop condition (refer to figure 3). 页面写入：128k/256k EEPROM能够进行64字节的页面写入。 页面写入的启动方式与字节写入相同，但在第一个数据字被锁定后，微控制器不发送ASTOP条件。 相反，在EEPROM确认收到第一个数据字后，微控制器可以发送多达63个更多的数据字。 在收到每个数据字后，EEPROM将以零响应。 微控制器必须以停止条件终止页面写入序列（参见图3）。
the data word address lower 6 bits are internally incremented following the receipt of eachdata word. the higher data word address bits are not incremented, retaining the memory pagerow location. when the word address, internally generated, reaches the page boundary, thefollowing byte is placed at the beginning of the same page. if more than 64 data words aretransmitted to the eeprom, the data word address will “roll over” and previous data will beoverwritten. the address “roll over” during write is from the last byte of the current page to thefirst byte of the same page. 数据字地址较低的6位在收到每个数据字后内部增加。较高的数据字地址位不会增加，保留内存页码位置。当内部生成的单词地址到达页面边界时，下面的字节被放置在同一页的开头。如果超过64个数据单词被转发到EOMA，数据单词地址将“滚动”，之前的数据将被覆盖。写过程中的地址“滚动”从当前页面的最后一个字节到同一个页面的第一个字节。
acknowledge polling: once the internally-timed write cycle has started and theeeprom inputs are disabled, acknowledge polling can be initiated. this involves sending astart condition followed by the device address word. the read/write bit is representative of theoperation desired. only if the internal write cycle has completed will the eeprom respondwith a zero, allowing the read or write sequence to continue. 元器件交易网www.cecb2b.com确认轮询：一旦内部定时写入周期启动并禁用EEPROM输入，就可以启动确认轮询。 这包括发送Astart条件，然后是设备地址字。 读/写位代表所需的操作。 只有当内部写入周期已经完成时，EEPROM才会以零响应，允许读或写序列继续。 元器件交易网www.cecb2b.com
read operations read operations are initiated the same way as write operations with the exception that theread/write select bit in the device address word is set to one. there are three read operations:current address read, random address read and sequential read. 读取操作读取操作的启动方式与写入操作相同，但设备地址字中的therad/write选择位被设置为一个。 有三种读取操作：当前地址读取、随机地址读取和顺序读取
current address read: the internal data word address counter maintains the lastaddress accessed during the last read or write operation, incremented by one. this addressstays valid between operations as long as the chip power is maintained. the address “rollover” during read is from the last byte of the last memory page, to the first byte of the firstpage. 当前地址读取：内部数据字地址计数器维护在最后一次读或写操作期间访问的lastAddress，递增1。 只要保持芯片功率，此地址在操作之间保持有效。 读取期间的地址“滚动”是从最后一个内存页面的最后一个字节到第一页的第一个字节。
once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the eeprom, the current address data word is serially clocked out. themicrocontroller does not respond with an input zero but does generate a following stop condi-tion (refer to figure 4). 一旦读/写选择位设置为一个的设备地址被EEPROM锁定并被识别边缘，当前地址数据字就会被串行锁定。 微控制器不响应输入零，但确实生成以下停止条件（参见图4）。
random read: a random read requires a “dummy” byte write sequence to load in the dataword address. once the device address word and data word address are clocked in andacknowledged by the eeprom, the microcontroller must generate another start condition.the microcontroller now initiates a current address read by sending a device address with theread/write select bit high. the eeprom acknowledges the device address and serially clocksout the data word. the microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to figure 5). 随机读取：随机读取需要一个“虚拟”字节写入序列来加载到dataword地址中。 一旦设备地址字和数据字地址被EEPROM锁定并被承认，微控制器必须生成另一个启动条件。微控制器现在通过发送具有Therad/写入选择位高的设备地址来启动当前地址读取。 EEPROM确认设备地址并串行时钟数据字。 微控制器不以零响应，但确实生成一个FOL-low停止条件（参见图5）。
sequential read: sequential reads are initiated by either a current address read or a ran-dom address read. after the microcontroller receives a data word, it responds with anacknowledge. as long as the eeprom receives an acknowledge, it will continue to incrementthe data word address and serially clock out sequential data words. when the memoryaddress limit is reached, the data word address will “roll over” and the sequential read will con-tinue. the sequential read operation is terminated when the microcontroller does not respondwith a zero but does generate a following stop condition (refer to figure 6). 顺序读取：顺序读取由当前地址读取或ran-dom地址读取启动。 在微控制器接收到一个数据字后，它用一个认知来响应。 只要EEPROM接收到确认，它将继续增加数据字地址，并串行地时钟出顺序数据字。 当内存地址限制达到时，数据字地址将“滚动”，顺序读取将连接。 当微控制器不以零响应，但生成以下停止条件时，顺序读取操作将终止（参见图6）。