FIR 是个比较复杂的 IP ,不同的设置需要不同的代码去配合。这篇文章详细介绍了这 FIR IP 设置需要注意的地方。 本文中介绍了五个实验，最基础的应用实验，FIR +FIFO实验，多通道多套系数配置实验，Reload Config 实验等，全面介绍了 FIR 的各种应用。所有实验提供 Vivado工程，Verilog代码下载，还有较为详细的文字图片介绍。

XILINX 官方 FIR 手册: https://docs.xilinx.com/v/u/en-US/pg149-fir-compiler 本文只介绍一些常用到的功能设置，和需要注意的地方。一些没介绍到的功能和细节请仔细阅读手册。

//am_modulation_dds.v
module	am_modulation_dds
(
	output			m_axis_data_tvalid,
	input			m_axis_data_tready,
	output	[15:0]	m_axis_data_tdata,
	input			rst_n,
	input			clk
);

	wire signed	[7:0]	dds_100khz_tdata_i;		//	100KHz   正弦波	AM 载波
	wire				dds_100khz_tvalid_i;
	wire				dds_100khz_tready_i;

	wire signed	[7:0]	dds_4khz_tdata_i;		//	4khz   正弦波	AM 调制信号
	wire				dds_4khz_tvalid_i;
	wire				dds_4khz_tready_i;

	reg signed	[15:0]	am_tdata_r;
	reg					am_tvalid_r;
	wire				am_tready_i;

	assign	am_tready_i			= m_axis_data_tready;
	assign	dds_100khz_tready_i	= am_tready_i;
	assign	dds_4khz_tready_i	= am_tready_i;

	assign	m_axis_data_tvalid	= am_tvalid_r;
	assign	m_axis_data_tdata	= am_tdata_r;

	always @(posedge clk)	//AM 调制算法实现
	begin
		if(rst_n == 0 )
		begin
			am_tdata_r	<= 0;
			am_tvalid_r	<= 0;
		end
		else if(am_tready_i == 1)
		begin
			am_tdata_r	<= dds_100khz_tdata_i * (dds_4khz_tdata_i/2 + 128);	// 128 是直流分量，式中的除2是为了不使数据超过16位溢出
																			// 这个代码中，载波频率很低，就直接用乘法去写代码了。
																			// 如果载波频率比较高就需要用DSP单元或乘法 IP 去实现。
			am_tvalid_r	<= dds_4khz_tvalid_i & dds_100khz_tvalid_i;
		end
	end

	dds_compiler_1m_100k dds1						// XILINX VIVADO DDS IP，1MHz 时钟输入，100KHz正弦波 8 位输出
	(
		.aclk				(clk),					// input wire aclk
		.aresetn			(rst_n),				// input wire aresetn
		.m_axis_data_tvalid	(dds_100khz_tvalid_i),	// output wire m_axis_data_tvalid
		.m_axis_data_tready	(dds_100khz_tready_i),	// input wire m_axis_data_tready
		.m_axis_data_tdata	(dds_100khz_tdata_i)	// output wire [7 : 0] m_axis_data_tdata
	);

	dds_compiler_1m_4k dds2							// XILINX VIVADO DDS IP，1MHz 时钟输入，4khz正弦波 8 位输出
	(
		.aclk				(clk),					// input wire aclk
		.aresetn			(rst_n),				// input wire aresetn
		.m_axis_data_tvalid	(dds_4khz_tvalid_i),	// output wire m_axis_data_tvalid
		.m_axis_data_tready	(dds_4khz_tready_i),	// input wire m_axis_data_tready
		.m_axis_data_tdata	(dds_4khz_tdata_i)		// output wire [7 : 0] m_axis_data_tdata
	);

endmodule

//am_demodulation_fir.v
module	am_demodulation_fir
(
	input					rst_n,
	input					clk,
	input					s_axis_data_tvalid,
	output					s_axis_data_tready,
	input	signed[15:0]	s_axis_data_tdata,
	output					m_axis_data_tvalid,
	input					m_axis_data_tready,
	output	signed[15:0]	m_axis_data_tdata
);


	reg 		[15:0]	abs_data_r	= 0;
	reg					abs_valid_r	= 0;
	wire				abs_tready_i;

	always @(posedge clk)
	begin
		if(rst_n == 0 )
			abs_valid_r	<= 0;
		else if(abs_tready_i == 1)
			abs_valid_r	<= s_axis_data_tvalid;
	end

	always @(posedge clk)	//取绝对值
	begin
		if(rst_n == 0 )
			abs_data_r	<= 0;
		else if(abs_tready_i == 1 && s_axis_data_tvalid == 1)
		begin
			if(s_axis_data_tdata >= 0)
				abs_data_r	<= s_axis_data_tdata;
			else
				abs_data_r	<= -s_axis_data_tdata;
		end
	end
	
	wire signed	[39:0]	fir_fm_tdata_i;
	wire				fir_fm_tvalid_i;
	wire				fir_fm_tready_i;

	assign	fir_fm_tready_i		= m_axis_data_tready;
	assign	m_axis_data_tdata	= fir_fm_tdata_i >>>19;
	assign	m_axis_data_tvalid	= fir_fm_tvalid_i;
	assign	s_axis_data_tready	= abs_tready_i;

	fir_compiler_lowpass_10k_30k_1m am_fir_u1
	(
		.aresetn			(rst_n),			// input wire aresetn
		.aclk				(clk),				// input wire aclk
		.s_axis_data_tvalid	(abs_valid_r),		// input wire s_axis_data_tvalid
		.s_axis_data_tready	(abs_tready_i),		// output wire s_axis_data_tready
		.s_axis_data_tdata	(abs_data_r),		// input wire [15 : 0] s_axis_data_tdata
		.m_axis_data_tvalid	(fir_fm_tvalid_i),	// output wire m_axis_data_tvalid
		.m_axis_data_tready	(fir_fm_tready_i),	// input wire m_axis_data_tready
		.m_axis_data_tdata	(fir_fm_tdata_i)	// output wire [39 : 0] m_axis_data_tdata
	);
endmodule

///////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

//am_modem_fir_testbench.v
module am_modem_fir_testbench;

reg			rst_n;
reg			clk;


parameter CLK_PERIOD		= 1000;		//1MHz

initial	begin
	rst_n = 0;
	#(20 * CLK_PERIOD)
	rst_n = 1;
	#(3000 * CLK_PERIOD)
	$stop;
end

initial
	clk = 0;
always
begin
	clk = #(CLK_PERIOD/2.0) ~clk;
end

	wire signed	[15:0]	am_mod_tdata;			//调幅波数据，载波100KHz 正弦波，调制信号 4KHz 正弦波
	wire				am_mod_tvalid;
	wire				am_mod_tready;

	wire signed	[15:0]	am_demod_tdata;			//经过解调还原的 4KHz 正弦波
	wire				am_demod_tvalid;
	wire				am_demod_tready=1;

	am_modulation_dds	am_u1					//调幅波调制模块，生成 载波100KHz 正弦波，调制信号 4KHz 正弦波的调幅信号
	(
		.clk				(clk),				//1MHz
		.rst_n				(rst_n),			//复位
		.m_axis_data_tdata	(am_mod_tdata),		//调幅波数据输出， output wire [16 : 0]
		.m_axis_data_tvalid	(am_mod_tvalid),
		.m_axis_data_tready	(am_mod_tready)
	);

	am_demodulation_fir		am_u2				//调幅波解调模块，将调幅波解调还原调制信号
	(
		.clk				(clk),				//1MHz
		.rst_n				(rst_n),			//复位
		.s_axis_data_tdata	(am_mod_tdata),		//调幅信号输入 intput wire [16 : 0]
		.s_axis_data_tvalid	(am_mod_tvalid),
		.s_axis_data_tready	(am_mod_tready),
		.m_axis_data_tdata	(am_demod_tdata),	//调幅波解调数据输出， output wire [16 : 0]
		.m_axis_data_tvalid	(am_demod_tvalid),
		.m_axis_data_tready	(am_demod_tready)
	);

endmodule

//fm_modulation_dds.v
module	fm_modulation_dds
(
	output			m_axis_data_tvalid,
	input			m_axis_data_tready,
	output	[15:0]	m_axis_data_tdata,
	input			rst_n,
	input			clk
);

	parameter			PHASE_COEF = 6554;//100KHz 


	reg signed	[15:0]	phase_cnt_r;

	wire signed	[15:0]	s_axis_phase_tdata_i;
	reg					s_axis_phase_tvalid_r;
	wire				s_axis_phase_tready_i;
	wire signed	[15:0]	phase_step_i;

	wire signed	[7:0]	dds_4khz_tdata_i;			//	4khz   正弦波	FM 调制信号
	wire				dds_4khz_tvalid_i;
	wire				dds_4khz_tready_i;

	wire signed	[15:0]	fm_tdata_i;					//	FM 调频波
	wire				fm_tvalid_i;
	wire				fm_tready_i;

	assign	phase_step_i 			= dds_4khz_tdata_i*16;
	assign	dds_4khz_tready_i		= s_axis_phase_tready_i;
	assign	s_axis_phase_tdata_i	= phase_cnt_r;
	

	always @(posedge clk)
	begin
		if(rst_n == 0 )
			s_axis_phase_tvalid_r	<= 0;
		else if(s_axis_phase_tready_i == 1)
			s_axis_phase_tvalid_r	<= dds_4khz_tvalid_i;
	end

	always @(posedge clk)
	begin
		if(rst_n == 0 )
		begin
			phase_cnt_r	<= 0;
		end
		else if(s_axis_phase_tready_i == 1 && dds_4khz_tvalid_i == 1)
		begin
			phase_cnt_r	<= phase_cnt_r + phase_step_i + PHASE_COEF;
		end
	end	
	
	dds_compiler_1m_4k dds1							// XILINX VIVADO DDS IP，100MHz 时钟输入，4khz正弦波 8 位输出
	(
		.aclk				(clk),					// input wire aclk
		.aresetn			(rst_n),				// input wire aresetn
		.m_axis_data_tvalid	(dds_4khz_tvalid_i),	// output wire m_axis_data_tvalid
		.m_axis_data_tready	(dds_4khz_tready_i),	// input wire m_axis_data_tready
		.m_axis_data_tdata	(dds_4khz_tdata_i)		// output wire [7 : 0] m_axis_data_tdata
	);

	
	dds_compiler_phase dds2
	(
		.aclk				(clk),						// input wire aclk
		.aresetn			(rst_n),					// input wire aresetn
		.s_axis_phase_tvalid(s_axis_phase_tvalid_r),	// input wire s_axis_phase_tvalid
		.s_axis_phase_tready(s_axis_phase_tready_i),	// output wire s_axis_phase_tready
		.s_axis_phase_tdata	(s_axis_phase_tdata_i),		// input wire [15 : 0] s_axis_phase_tdata
		.m_axis_data_tvalid	(fm_tvalid_i),				// output wire m_axis_data_tvalid
		.m_axis_data_tready	(fm_tready_i),				// input wire m_axis_data_tready
		.m_axis_data_tdata	(fm_tdata_i)				// output wire [15 : 0] m_axis_data_tdata
	);
	
	assign	fm_tready_i			= m_axis_data_tready;
	assign	m_axis_data_tvalid	= fm_tvalid_i;
	assign	m_axis_data_tdata	= fm_tdata_i;

endmodule