module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); wire es1,em0,em1,eh0,eh1; // enables of some instances wire rs1,rm1; // reset of some instances bcd_counter s0 (clk, reset, ena, ss[3:0]); // one of second bcd_counter s1 (clk, rs1, es1, ss[7:4]); // ten of second bcd_counter m0 (clk, reset, em0, mm[3:0]); // one of minute bcd_counter m1 (clk, rm1, em1, mm[7:4]); // ten of minute bcd_counterh0 h0 (clk, reset, eh0, hh[7:4], hh[3:0]); // one of hour bcd_counterh1 h1 (clk, reset, eh1, hh[7:4]); // ten of hour assign es1 = (ss[3:0] == 9 ? 1 : 0) && ena; assign rs1 = (ss == 8'h59 ? 1 : 0) && ena; assign rs1 = (ss == 8'h59 ? 1 : 0) || reset; // second assign em0 = ((ss == 8'h59) ? 1 : 0) && ena; assign em1 = (mm[3:0] == 9 && ss == 8'h59) && ena; assign rm1 = (mm == 8'h59 && ss == 8'h59) || reset; assign eh0 = (mm == 8'h59 && ss == 8'h59) && ena; assign eh1 = ((hh[3:0] == 9 || hh == 8'h12) && mm == 8'h59 && ss == 8'h59) && ena; always @(posedge clk) begin // cotrol of pm if (reset) pm <= 0; else begin if (hh == 8'h11 && mm == 8'h59 && ss == 8'h59 ) pm <= ~pm; else pm <= pm; end end endmodule module bcd_counter ( // basic decade counter for s0,s1,m0,m1 input clk, input reset, // Synchronous active-high reset input enable, // Synchronous active-high enable output [3:0] q); always @(posedge clk) begin if (reset || (q == 9 && enable == 1)) begin q <= 0; end else begin if (enable) q <= q 1; else q <= q; end end endmodule module bcd_counterh0 ( // special counter for the one of hour input clk, input reset, // Synchronous active-high reset input enable, // Synchronous active-high enable input [3:0] p, output [3:0] q); always @(posedge clk) begin if (reset ) q <= 2; else begin if (q == 9 && enable) q <= 0; else begin if (p == 1 && q == 2 && enable) q <= 1; else begin if (enable) q <= q 1; else q <= q; end end end end endmodule module bcd_counterh1 ( // special counter for the ten of hour input clk, input reset, // Synchronous active-high reset input enable, // Synchronous active-high enable output [3:0] q); always @(posedge clk) begin if (reset ) q <= 1; else begin if (q == 1 && enable) q <= q -1; else begin if (q == 0 && enable) q <= q 1; else q <= q; end end end endmodule