检测1101，如果是，输出1，否则输出0；
标准的源代码MOORE三级状态机。
源代码：
module detect1101( //input clk, rst_n, in, //output out ); input clk,rst_n,in; output reg out; //parameter define parameter S0 = 5'b00001, S1 = 5'b00010, S2 = 5'b00100, S3 = 5'b01000, S4 = 5'b10000; //reg define reg[4:0] current_state,next_state; //first always @(posedge clk or negedge rst_n) begin if(!rst_n) current_state = S0; else current_state = next_state; end //second always @(posedge clk or negedge rst_n) begin if(!rst_n) next_state = S0; else begin case(current_state) S0: begin if(in == 1) next_state = S1; else next_state = S0; end S1: begin if(in == 1) next_state = S2; else next_state = S0; end S2: begin if(in == 1) next_state = S2; else next_state = S3; end S3: begin if(in == 1) next_state = S4; else next_state = S0; end S4: begin if(in == 1) next_state = S2; else next_state = S0; end endcase end end //third always @(current_state) begin case(current_state) S0:out = 0; S1:out = 0; S2:out = 0; S3:out = 0; S4:out = 1; endcase end endmodule测试代码：使用{$random} % b用于生成随机数
`timescale 1 ns/ 1 ns module detect1101_vlg_tst(); // constants // general purpose registers //reg eachvec; // test vector input registers reg clk; reg in; reg rst_n; // wires wire out; // assign statements (if any) detect1101 i1 ( // port map - connection between master ports and signals/registers .clk(clk), .in(in), .out(out), .rst_n(rst_n) ); initial begin clk = 1'b0; rst_n = 1'b0; in = 1'b0; #100 rst_n = 1'b1; //#20 in = 1'b1; //#20 in = 1'b0; //#20 in = 1'b1;; // code that executes only once // insert code here --> begin // --> end $display("Running testbench"); end always #10 clk = ~clk; always #20 in = {$random} % 2; //always // optional sensitivity list // @(event1 or event2 or ... eventn) //begin // code executes for every event on sensitivity list // insert code here --> begin //@eachvec; // --> end //end endmodule 仿真结果：