LTC4307CMS8-1#PBF

LINEAR TECHNOLOGY  LTC4307CMS8-1#PBF  芯片, 总线缓冲器, 热插拔, 2线式, 8MSOP

The is a 2-wire Bus Buffer that provides capacitance buffering between input and output. The HDMI specification requires that devices have less than 50pF of input capacitance on their DDC bus lines. The LTC4307-1"s capacitance buffering feature, in conjunction with its sub-10pF data and clock input capacitance, allows HDMI components to easily meet the 50pF requirement and tolerate high capacitance on the internal bus. The buffer also provides level-shifting between 3.3 and 5V systems to allow lower voltage HDMI transmitters, receivers and EEPROM to interface to the 5V DDC bus. READY is an open-drain digital output flag that indicates whether or not the input and output busses are connected and can interface to the HDMI hot plug detect HPD signal. When driven high, the ENABLE digital input allows the buffer to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between the input and output busses.

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Bidirectional buffer for display data channel DDC

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Compliant with HDMI specification version 1.3 DDC capacitance requirement

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±5kV Human body model ESD Protection

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60mV Buffer offset independent of load

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Compatible with non-compliant VOL I²C devices

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Isolates input SDA and SCL line from output

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Compatible with I²C, I²C fast mode and SMBus

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READY Open-drain output