CDCV855

1:4 DDR PLL 时钟驱动器

The is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair CLK, CLK\\ to four differential pairs of clock outputs Y[0:3], Y[0:3]\\ and one differential pair of feedback clock outputs FBOUT, FBOUT\\. When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state 3-state, and the PLL is shut down low-power mode. The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz typical 10 MHz. An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.

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Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications

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Spread Spectrum Clock Compatible

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Operating Frequency: 60 MHz to 180 MHz

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Low Jitter cyc–cyc: ±50 ps

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Distributes One Differential Clock Input to Four Differential Clock Outputs

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Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low

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Operates From Dual 2.5-V Supplies

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28-Pin TSSOP Package

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Consumes < 200-µA Quiescent Current

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External Feedback PIN FBIN, FBIN\\ Are Used to Synchronize the Outputs to the Input Clocks