CY7C1381D-133AXI

18兆位（ 512K的× 36/1米× 18 ）流过SRAM 18 Mbit 512 K × 36/1 M × 18 Flow Through SRAM

SRAM - 同步，SDR 存储器 IC 18Mb（512K x 36） 并联 133 MHz 6.5 ns 100-TQFP（14x20）

得捷:
IC SRAM 18MBIT PARALLEL 100TQFP

艾睿:
SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 6.5ns 100-Pin TQFP Tray

安富利:
The CY7C1381D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns 133-MHz version. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK. The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 [2], Burst Control inputs ADSC, ADSP, and ADV, Write Enables BWx, and BWE, and Global Write GW. Asynchronous inputs include the Output Enable OE and the ZZ pin.The CY7C1381D allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV.The CY7C1381D operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Chip1Stop:
SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 6.5ns 100-Pin TQFP Tray

DeviceMart:
IC SRAM 18MBIT 133MHZ 100LQFP

Win Source:
IC SRAM 18MBIT 133MHZ 100TQFP