ADC12DL066

具有内部参考的双路 12 位、66 MSPS、450 MHz 输入带宽 A/D 转换器

The is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second Msps, minimum. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance and a 450 MHz Full Power Bandwidth. Operating on a single 3.3V power supply, the ADC12DL066 achieves 10.7 effective bits and consumes just 686 mW at 66 Msps, including the reference current. The Power Down feature reduces power consumption to 75 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or two’s complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL066 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

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Choice of Binary or 2’s Complement Output Format

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Single +3.3V Supply Operation

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Outputs 2.4V to 3.3V Compatible

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Pin Compatible with ADC12D040

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Power Down Mode

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Internal/External Reference

## Key Specifications

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Resolution: 12 Bits

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DNL: ±0.5 LSB typ

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SNR fIN = 10 MHz: 66 dB typ

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SFDR fIN = 10 MHz: 81 dB typ

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Power Consumption

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Operating: 686 mW typ

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Power Down Mode: 75 mW typ