SN74LV00D

四路2输入正与非门 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

description

These quadruple 2-input positive-NAND gates are designed for 2.7-V to 5.5-V VCCoperation.

EPIC™ Enhanced-Performance Implanted CMOS 2-µ Process

Typical VOLPOutput Ground Bounce < 0.8 V at VCC, TA= 25°C

Typical VOHVOutput VOHUndershoot > 2 V at VCC, TA= 25°C

ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model C = 200 pF, R = 0

Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17

Package Options Include Plastic Small-Outline D, Shrink Small-Outline DB, Thin Shrink Small-Outline PW, Ceramic Flat W Packages, Chip Carriers FK, and J 300-mil DIPs