TLV320AIC11

通用低输入/输出电压的 16 位 22-KSPS DSP 编解码器

The provides high resolution signal conversion from digital-to-analog D/A and from analog-to-digital A/D using oversampling sigma-delta technology. It allows 2-to-1 MUX inputs with built-in antialiasing filter and amplification for general-purpose applications such as telephone hybrid interface, electret microphone preamp, etc. Both IN and AUX inputs accept normal analog signals. This device consists of a pair of 16-bit synchronous serial conversion paths one for each direction, and includes an interpolation filter before the DAC and a decimation filter after the ADC. The FIR filters can be bypassed to offer flexibility and power savings. Other overhead functions provided on-chip include timing programmable sample rate, continuous data transfer, and FIR bypass and control programmable-gain amplifier, communication protocol, etc.. The sigma-delta architecture produces high-resolution analog-to-digital and digital-to-analog conversion at low system cost.

The TLV320AIC11 design enhances communication with the DSP. The continuous data transfer mode fully supports ’s DSP autobuffering ABU to reduce DSP interrupt service overhead. The automatic cascading detection ACD makes cascade programming simple and supports a cascade operation of one master and up to seven slaves. The direct-configuration mode for host interface uses a single-wire serial port to directly program internal registers without interference from the data conversion serial port, or without resetting the entire device. The event monitor mode allows the DSP to monitor external events like telephone’s ring and off-hook detection.

In the lower-power mode, the TLV320AIC11 converts data at a sampling rate of 8 KSPS consuming only 39 mW.

The programmable functions of this device are configured through a serial interface that can be gluelessly interfaced to any DSP that accepts 4-wire serial communications, such as the TMS320UC54x. The options include software reset, device power-down, separate control for ADC and DAC turnoff, communications protocol, signal-sampling rate, gain control, and system-test modes. See Appendix A for further details.

The TLV320AIC11 is particularly suitable for a variety of applications in hands-free car kits, VOIP, cable modem, speech, and telephony area including low-bit rate, high-quality compression, speech enhancement, recognition, and synthesis. Its low-group delay characteristic makes it suitable for single or multichannel active-control applications.

The wide range of low-voltage I/O 1.1 V–3.6 V enables the AIC11 to interface with a single power supply, or with dual power supplies for mixed low-voltage DSP systems such as the TMS320UC54x. This feature eliminates the need for external level-shifting and reduces power consumption.

The TLV320AIC11 is characterized for commercial operation from 0°C to 70°C, and industrial operation from –40°C to 85°C.

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16-bit oversampling sigma-delta A/D converter

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16-bit oversampling sigma-delta D/A converter

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Maximum output conversion rate:

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22 ksps with on-chip FIR filter

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88 ksps with FIR bypassed

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Voiceband bandwidth in FIR-bypassed mode and final sampling rate at 8 ksps

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90-dB SNR/ADC and 87-dB SNR/DAC with DSP’s FIR FIR bypassed @ 88 ksps/5 V

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87-dB SNR/ADC and 85-dB SNR/DAC with DSP’s FIR FIR bypassed @ 88 ksps/3.3 V

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On-chip FIR produced 84-dB SNR for ADC and 85-dB SNR for DAC over 11-kHz BW

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Built-in functions including PGA, antialiasing analog filter, and operational amplifiers for general-purpose interface such as MIC interface and hybrid interface

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Glueless serial port interface to DSPs TI TMS320UC54x or standard DSPs

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Automatic cascading detection ACD makes cascade programming simple and allows up to 8 devices to be connected in cascade.

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On-fly reconfiguration modes include secondary-communication mode and direct-configuration mode host interface.

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Continuous data-transfer mode for use with autobuffering ABU to reduce DSP interrupt service overhead

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Event-monitor mode provides external-event control, such as RING/OFF-HOOK detection

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Programmable ADC and DAC conversion rate

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Programmable input and output gain control

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Separate software control for ADC and DAC power-down

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Low-voltage DVDD1 1.1-V to 3.6-V digital I/O

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Analog AVDD1 and AVDD2 3 V to 5.5 V core power supply

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Digital DVDD2 3 V to 5.5 V core power supply

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Power dissipation PD of 39 mW typical for 8-ksps at 3.3 V

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Hardware power-down mode to 0.2 mW

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Internal and external reference voltage Vref

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Differential and single-ended analog input/output

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2s-complement data format

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Test mode, which includes digital loopback and analog loopback

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600- output driver