CD74HC191

高速 CMOS 逻辑可预设的同步 4 位二进制加/减计数器

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs A–D is accomplished by a low asynchronous parallel load LOAD\ input. Counting occurs when LOAD\ is high, count enable CTEN\ is low, and the down/up D/U input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading see Figure 1. The MAX/MIN output also initiates the ripple clock RCO\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ see Figure 2.

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams see Figure 3.

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2-V to 6-V VCC Operation ’HC190,191

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4.5-V to 5.5-V VCC Operation ’HCT191

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Wide Operating Temperature Range of –55 to 125°C

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Synchronous Counting and Asynchronous Loading

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Two Outputs for n-Bit Cascading

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Look-Ahead Carry for High-Speed Counting

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Balanced Propagation Delay and Transition Times

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Standard Outputs Drive Up To 15 LS-TTL Loads

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Significant Power Reduction Compared to LS-TTL Logic ICs