CDCM6208V1FRGZT

2:8 超低功耗、低抖动时钟发生器，引脚模式型号 F 48-VQFN -40 to 85

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an

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*_innovative_** fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In

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*_synthesizer mode_**, the overall output jitter performance is less than 0.5 ps-rms 10 k – 20 MHz or 20 ps-pp unbound on output using integer dividers and is between 50 to 220 ps-pp 10 k – 40 MHz on outputs using fractional dividers depending on the prescaler output frequency.

In

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*_jitter cleaner mode_**, the overall output jitter is less than 2.1 ps-rms 10 k – 20 MHz or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.