CK-K7-KC724-G-J

表征套件, Kintex-7 FPGA, Vivado, 仅限日本

The from is a 7 FPGA KC724 characterization kit Japan specific. The Kintex®-7 FPGA KC724 characterization kit provides the hardware environment for characterizing and evaluating 16 GTX 12.5Gbps transceivers of the on-board Kintex-7 K325T FPGA. The KC724 allows evaluation of the Integrated Bit Error Ratio Test IBERT demonstration using either the Vivado® or ISE® design suite. Each GTX quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTX Quad, four transmit/receive pairs as well as the two independent reference clocks enabling the highest level of flexibility in testing custom applications.

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Hardware, design tools, IP and pre-verified reference designs

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Integrated Bit Error Ratio Test IBERT reference design

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Expand I/O with the FPGA Mezzanine Card FMC interface

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BullsEye connector supporting a full GTX quad with four transmit/receive pairs

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System ACE™ SD controller, 326080 logic cells, 840 DSP slices, 16020Kb memory

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Four Samtec BullsEye connector pads for the GTX transceivers and reference clocks

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Two pairs of differential MRCC inputs with SMA connectors

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Power status LEDs, general purpose DIP switches, LEDs, push buttons and test I/O display

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Digilent USB JTAG programming port configuration

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Fixed, 200MHz 2.5V LVDS oscillator wired to multi region clock capable MRCC inputs clocking