LPC1765FBD100

NXP  LPC1765FBD100  微控制器, 32位, ARM 皮质-M3, 100 MHz, 256 KB, 64 KB, 100 引脚, LQFP

The is a 32-bit Microcontroller based on ARM Cortex-M3 core with RISC architecture operates at a maximum frequency of 100MHz. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The device incorporates 256kB internal flash, 64kB internal RAM, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 8-channel 12-bit A/D converter, 10-bit D/A converter, motor control PWM, quadrature encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power real-time clock RTC with separate battery supply and 70 general-purpose I/O pins.

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ARM Cortex-M3 built-in nested vectored interrupt controller NVIC

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In-system programming ISP and In-application programming IAP

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Multilayer AHB matrix interconnect

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Split APB bus

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Standard JTAG debug interface for compatibility

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Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution

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Integrated PMU power management unit

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Four reduced power modes - Sleep, deep-sleep, power-down and deep power-down

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Four external interrupt inputs configurable as edge/level sensitive

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Non-maskable Interrupt NMI input

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The wake-up interrupt controller WIC

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Brownout detect with separate threshold for interrupt and forced reset

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Power-on reset POR

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Crystal oscillator with an operating range of 1MHz to 25MHz

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4MHz Internal RC oscillator trimmed to 1 % accuracy

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PLL allows CPU operation up to the maximum CPU rate

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USB PLL for added flexibility

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Code read protection CRP with different security levels

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Unique device serial number for identification purposes