ADS62C15

具有 SNRBoost 的双通道 11 位 125MSPS ADC

is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist, Fs/2. It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction in steps of 0.05 dB, decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS Double Data Rate. ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range –40°C to 85°C.

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Maximum Sample Rate: 125 MSPS

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11-Bit Resolution With No Missing Codes

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82 dBc SFDR at Fin = 117 MHz

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67 dBFS SNR at Fin = 117 MHz

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77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth

using technology

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92 dB Crosstalk

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Parallel CMOS and DDR LVDS Output Options

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3.5 dB Coarse Gain and Programmable Fine Gain

up to 6 dB for SNR/SFDR Trade-Off

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_Digital Processing Block_ With:

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Offset Correction

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Fine Gain Correction, in Steps of 0.05 dB

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Decimation by 2/4/8

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Built-in and Custom Programmable 24-Tap Low/High/

Band Pass Filters

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Supports Sine, LVPECL, LVDS and LVCMOS Clocks and

Amplitude Down to 400 mVPP

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Clock Duty Cycle Stabilizer

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Internal Reference; Also Supports External Reference

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64-QFN Package 9mm × 9mm