74AHCT138D,118

NXP  74AHCT138D,118  芯片, 解码器/信号分离器, 3:8, SOIC-16

The 74AHCT138D is a 3-to-8 line Decoder/Demultiplexer pin compatible with low power Schottky TTL LSTTL. It accepts three binary weighted address inputs A0, A1 and A2 and, when enabled, provides eight mutually exclusive outputs Y0\ to Y7\\ that are low when selected. There are three enable inputs: two active low E1\ and E2\\ and one active high E3. Every output will be high unless E1\ and E2\ are low and E3 is high. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 5 lines to 32 lines decoder with just four 74AHCT138 devices and one inverter. It can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active high or low state.

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Balanced propagation delays

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All inputs have Schmitt-trigger action

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Demultiplexing capability

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Multiple input enable for easy expansion

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Ideal for memory chip select decoding

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Inputs accepts voltages higher than VCC

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Operates with TTL input levels

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Complies with JEDEC standard No. 7A