预置Divdie - N计数器 Presettable Divdie-By-N Counter
The contains five Johnson counter stages which are asynchronously presettable and resettable. The counters are synchronous, and increment on the positive going edge of the clock. Presetting is accomplished by a logic 1 on the preset enable input. Data on the Jam inputs will then be transferred to their respective Qbar outputs inverted. A logic 1 on the reset input will cause all Qbar outputs to go to a logic 1 state. Division by any number from 2 to 10 can be accomplished by connecting appropriate Qbar outputs to the data input, as shown in the Function Selection table. Anti-lock gating is included in the MC14018B to assure proper counting sequence.
Features
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| 型号 | 品牌 | 下载 |
|---|---|---|
| MC14018B | ON Semiconductor 安森美 | 下载 |
| MC14049BDG | ON Semiconductor 安森美 | 下载 |
| MC14049UBDR2G | ON Semiconductor 安森美 | 下载 |
| MC14600P | Freescale 飞思卡尔 | 下载 |
| MC14050BDG | ON Semiconductor 安森美 | 下载 |
| MC14578P | Freescale 飞思卡尔 | 下载 |
| MC14015BDR2 | ON Semiconductor 安森美 | 下载 |
| MC14024BDR2 | Motorola 摩托罗拉 | 下载 |
| MC14490DWG | ON Semiconductor 安森美 | 下载 |
| MC14094BDG | ON Semiconductor 安森美 | 下载 |
| MC14060BDG | ON Semiconductor 安森美 | 下载 |