SN74LVC112ADR

双负边沿触发的JK触发器具有清零和预设 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

得捷:
IC FF JK TYPE DUAL 1BIT 16SOIC

立创商城:
SN74LVC112ADR

德州仪器TI:
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

艾睿:
Are you looking to store information at a basic level? The SN74LVC112ADR flip flop device from Texas Instruments can easily save state information. It has a differential output signal. This flip flop has a minimum operating temperature of -40 °C and a maximum of 125 °C. This product will be shipped in tape and reel packaging for quick mounting and safe delivery. It has 2 channels per chip. This inverting/non-inverting device has a typical operating supply voltage of 1.8|2.5|3.3 V. Its minimum operating supply voltage of 1.65 V, while its maximum is 3.6 V.

安富利:
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC T/R

Verical:
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC T/R

Win Source:
IC JK TYPE NEG TRG DUAL 16SOIC