CD54HC4514

带输入锁存器的高速 CMOS 逻辑 4 至 16 线路解码器/多路解复用器

The , CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input E\\. A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs A0-A3 as addresses. This E\ input also serves as a chip select when these devices are cascaded.

When Latch Enable LE\\ is high the output follows changes in the inputs see truth table. When LE is low the output is isolated from changes in the input and remains at the level high for the 4514, low for the 4515 it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads.

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Multifunction Capability

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Binary to 1-of-16 Decoder

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1-to-16 Line Demultiplexer

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Fanout Over Temperature Range

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Standard Outputs . . . . . . . 10 LSTTL Loads

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Bus Driver Outputs . . . . 15 LSTTL Loads

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Wide Operating Temperature Range . . . -55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V