AD5752RBREZ-REEL7

完成后，双通道， 12位/ 14位/ 16位，串行输入，单极性/双极性，电压输出DAC Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

Product Details

The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit, serial input, voltage output digital-to-analog converters. They operate from single supply voltages of +4.5 V up to +16.5 V or dual supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale output range is software selectable from +5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided.

The parts offer guaranteed monotonicity, integral nonlinearity INL of ±16 LSB maximum, low noise, 10 μs maximum settling time, and an on-chip +2.5 V reference.

The AD5722R/AD5732R/AD5752R use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output depending on the state of Pin BIN/2sComp, and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range.

**Applications**

* Industrial automation

* Closed-loop servo control, process control

* Automotive test and measurement

* Programmable logic controllers

### Features and Benefits

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Complete, dual, 12-/14-/16-bit digital-to-analog converter DAC

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Operates from single/dual supplies

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Software programmable output range

+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V

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INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum

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Total unadjusted error TUE: 0.1% FSR maximum

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Settling time: 10 μs typical

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Integrated reference: 5 ppm/°C maximum

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Integrated reference buffers

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Output control during power-up/brownout

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Simultaneous updating via LDAC

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Asynchronous CLR to zero scale or midscale

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See data sheet for additional features