SN65LVDM176

半双工 LVDM 收发器

The is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling LVDS to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to A/EIA-644 standard compliant devices SN65LVDS counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.

The SN65LVDM176 is characterized for operation from \x9640°C to 85°C.

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Low-Voltage Differential Driver and Receiver for Half-Duplex Operation

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Designed for Signaling Rates of 400 Mbit/s

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ESD Protection Exceeds 15 kV on Bus Pins

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Operates From a Single 3.3-V Supply

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Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 50- Load

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Valid Output With as Little as 50 mV Input Voltage Difference

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Propagation Delay Times

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Driver: 1.7 ns Typ

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Receiver: 3.7 ns Typ

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Power Dissipation at 200 MHz

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Driver: 50 mW Typical

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Receiver: 60 mW Typical

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LVTTL Levels Are 5-V Tolerant

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Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V

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Open-Circuit Fail-Safe Receiver

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Surface-Mount Packaging

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D Package SOIC

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DGK Package MSOP

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