ENC624J600-I/PT

MICROCHIP  ENC624J600-I/PT  以太网控制器, 10 Mbps, IEEE 802.3, 3 V, 3.6 V, TQFP, 64 引脚

The is a stand-alone 10/100 Base-T Ethernet Interface Controller with integrated MAC and PHY, hardware cryptographic security engines and factory pre-programmed unique MAC address. A 24kB on-chip RAM buffer is for TX and RX operations. The ENC624J600 have an industry standard serial peripheral interface SPI or a flexible parallel interface. It is designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port. The ENC624J600 devices meet all of the IEEE 802.3 specifications applicable to 10Base-T and 100Base-TX Ethernet, including many optional clauses, such as auto-negotiation. It incorporates a number of packet filtering schemes to limit incoming packets.

.

IEEE 802.3™ compliant fast Ethernet controller

.

Integrated MAC and 10/100Base-T PHY

.

Hardware security acceleration engines

.

24kB transmit/receive packet buffer SRAM

.

Supports one 10/100Base-T port with automatic

.

Polarity detection and correction

.

Supports auto-negotiation

.

Support for pause control frames, including automatic transmit and receive flow control

.

Supports half and full-duplex operation

.

Programmable automatic re-transmit on collision

.

Programmable padding and CRC generation

.

Programmable automatic rejection of erroneous and runt packets

.

Factory pre-programmed unique MAC address

.

MAC support for uni-cast, multicast and broadcast packet

.

Physical layer - wave shaping output filter

.

Security engines - Software AES CTR mode capability

.

Buffer - configurable transmit/receive buffer size

.

Operational - Transmit and receive interrupts

ESD sensitive device, take proper precaution while handling the device.