SN74BCT573N

八路透明D类锁存器具有三态输出 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

The is an octal transparent D Latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data D inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state high or low logic levels or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.

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State-of-the-Art BiCMOS design

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Significantly reduces ICCZ

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Full parallel access for loading