TLK1002A

二路信号调节收发器

is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop PLL generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.

Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.

The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop PLL circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.

TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.

Advanced low power CMOS design leads to low power consumption.

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Fully Integrated Signal Conditioning

Transceiver

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1.0-1.3 Gbps Operation

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Low Power CMOS Design <300 mW

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High Differential Output Voltage Swing 1600 mVp-p typical

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400 mVp-p Differential Input Sensitivity

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High Input Jitter Tolerance 0.606 UI

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Single 1.8 V Power Supply

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2.5 V Tolerant Control Inputs

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Differential VML Transmit Outputs With No External Components Necessary

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No External Filter Components Required for PLLs

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Supports Loop-Back Modes

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Temperature Rating 0°C to 70°C

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Small Footprint 4 mm × 4 mm 24-Lead QFN Package

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APPLICA ONS

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Resynchronization in Both Directions for 1.25 Gbps Links

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Repeater for 1.0625 Gbps Applications