MPC8260AVVPJDB

MPU PowerQUICC II MPC82xx Processor RISC 32Bit 0.25um 300MHz 3.3V 480Pin TBGA Tray

Overview

The MPC8260 PowerQUICC® II™ is an advanced integrated communications processor designed for the telecommunications and networking markets.

The MPC8260 now offers floating point support.

The MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC®, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.

Like the MPC860, the MPC8260 integrates two main components, the embedded G2 core and the Communications Processor Module CPM. This dual-processor architecture consumes less power than traditional architectures because the CPM offloads peripheral tasks from the embedded G2 core. The CPM simultaneously supports three fast serial communications controllers FCCs, two multichannel controllers MCCs, four serial communications controllers SCCs, two serial management controllers SMCs, one serial peripheral interface SPI and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the MPC8260, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.

"Products MPC8260ACVVMHBB, MPC8260ACVVMIBB, MPC8260ACZUMHBB, MPC8260ACZUMIBB, MPC8260AVVMHBB, MPC8260AVVPIBB, , MPC8260AZUMHBB, MPC8260AZUPIBB, and MPC8260AZUPJDB on this page are Not Recommended for New Designs".

MoreLess

## Features

System core microprocessor supporting frequencies of 133-300 MHz

* 190 MIPS at 100 MHz Dhrystone 2.1

* 505 MIPS at 266 MHz Dhrystone 2.1

* 570 MIPS at 300 MHz Dhrystone 2.1

* High-performance, superscalar microprocessor

* Disable CPU mode

* Supports the ® external L2 cache chip MPC2605

* Improved low-power core

* 16 Kbyte data and 16 Kbyte instruction cache, four-way set associative

* Memory Management Unit

* Floating point unit enabled

* Common on-chip processor COP

* System Integration Unit SIU

* Memory Controller, including two dedicated SDRAM machines

* PCI up to 66 MHz available in subsequent versions

* Hardware bus monitor and software watchdog timer

* IEEE 1149.1 JTAG test access port

* High-Performance Communications Processor Module CPM with operating frequency up to 133, 166, or 200 MHz

* G2 core and CPM may run at different frequencies

* Parallel I/0 Registers

* On-board 32 KBytes of dual-port RAM

* Two multi-channel controllers MCCs each supporting 128 full-duplex, 64 Kbps, HDLC lines

* Virtual DMA Functionality

* Three FCCs supporting:

* Up to 155 Mbps ATM SAR maximum of two AAL0, AAL1, AAL2, AAL5

* 10/100 Mbps Ethernet up to three IEEE 802.3X with Flow Control

* 45 Mbps HDLC/Transparent up to three

* Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus

* Two UTOPIA level-2 master/slave ports, both with multi-PHY support.

* Three MII Interfaces

* Eight TDM interfaces T1/E1, two TDM ports can be glueless to T3/E3

* 1.8V or 2.0V internal and 3.3V I/O

* 300 MHz power consumption: 2.5 W

* 480 TBGA package 37.5 mm x 37.5 mm

## Features Comparison Table

### MPC8260 Derivatives

| 8250 | 8255 | 8260 | 8264 | 8265 | 8266

\---|---|---|---|---|---|---

**IMA Functionality** | - | - | - | Yes | - | Yes

**UTOPIA II Ports** | 0 | 2 | 2 | 2 | 2 | 2

**PCI Interface** | Yes | - | - | - | Yes | yes

**Multi-Channel HDLC** | Up to 128 | Up to 128 | Up to 256 | Up to 256 | Up to 256 | Up to 256

**I-Cache Kbyte** | 16 | 16 | 16 | 16 | 16 | 16

**Fast Communication Controllers FCCs** | 3 | 2 | 3 | 3 | 3 | 3

**Serial Communications Controllers SCCs** | 4 | 4 | 4 | 4 | 4 | 4

**D-Cache Kbyte** | 16 | 16 | 16 | 16 | 16 | 16

**Ethernet 10/100** | Up to 3 | Up to 2 | Up to 3 | Up to 3 | Up to 3 | Up to 3

**Ethernet 10T** | Up to 4 | Up to 4 | Up to 4 | Up to 4 | Up to 4 | Up to 4

### PowerQUICC II Masks and Versions

| IMMR_ [16-31]1 | Rev_Num2 | Qualification | Revision | Process | Mask

\---|---|---|---|---|---|---

**MPC8260 Family** | | | XC | A.1

B.3

C.2 | 0.29 µm

HiP3 | 0K26N

3K23A

6K23A, 7K23A

**MPC8260 Family** | | | XC

MC

MC | A.0

B.1

C.0 | 0.25 µm

HiP4 | 2K25A

4K25A

5K25A

**MPC8280 Family** | | | -

MC

MC | 0

0.1

A.0 | 0.13 µm

HiP7 | 0K49M

1K49M

2K49M, 3K49M

**MPC8272 Family** | | | PC

MC | 0

A.0 | 0.13 µm

HiP7 | 0K50M

1K50M

Notes:

1\\. The IMMR[16-31] indicates the mask number.

2\\. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.

3 . Encryption Enabled.

4 . Encryption Disabled.

Masks and versions table last updated on 14OCT2004.