TMS320DM6443

DaVinci 数字媒体片上系统

The also referenced as DM6443 leverages "s Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer RISC technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

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A coprocessor 15 CP15 and protection module

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Data and program Memory Management Units MMUs with table look-aside buffers.

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Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag VIVT.

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word VLIW architecture developed by Texas Instruments TI, making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second MIPS at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units ALUs. The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates MACs per cycle for a total of 2376 million MACs per second MMACS, or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the _TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide_ literature number SPRU732.

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache L1P is a 256K-bit direct mapped cache and the Level 1 data cache L1D is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache L2 consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC EMAC with a Management Data Input/Output MDIO module; an inter-integrated circuit I2C Bus interface; one audio serial port ASP; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output GPIO with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator PWM peripherals; and 2 external memory interfaces: an asynchronous external memory interface EMIFA for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System VPSS that has a configurable Resizer and Video Processing Back-End VPBE output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End VPBE is comprised of an On-Screen Display Engine OSD and a Video Encoder VENC. The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller EMAC provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second Mbps and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service QOS support.

The Management Data Input/Output MDIO module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!

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High-Performance Digital Media SoC

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594-MHz C64x+™ Clock Rate

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297-MHz ARM926EJ-S™ Clock Rate

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Eight 32-Bit C64x+ Instructions/Cycle

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4752 C64x+ MIPS

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Fully Software-Compatible With C64x /ARM9™

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Advanced Very-Long-Instruction-Word VLIW TMS320C64x+™ DSP Core

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Eight Highly Independent Functional Units

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Six ALUs 32-/40-Bit, Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

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Two Multipliers Support Four 16 x 16-Bit Multiplies 32-Bit Results per Clock Cycle or Eight 8 x 8-Bit Multiplies 16-Bit Results per Clock Cycle

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Load-Store Architecture With Non-Aligned Support

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64 32-Bit General-Purpose Registers

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Instruction Packing Reduces Code Size

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All Instructions Conditional

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Additional C64x+™ Enhancements

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Protected Mode Operation

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Exceptions Support for Error Detection and Program Redirection

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Hardware Support for Modulo Loop Operation

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C64x+ Instruction Set Features

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Byte-Addressable 8-/16-/32-/64-Bit Data

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8-Bit Overflow Protection

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Bit-Field Extract, Set, Clear

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Normalization, Saturation, Bit-Counting

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Compact 16-Bit Instructions

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Additional Instructions to Support Complex Multiplies

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C64x+ L1/L2 Memory Architecture

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32K-Byte L1P Program RAM/Cache Direct Mapped

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80K-Byte L1D Data RAM/Cache 2-Way Set-Associative

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64K-Byte L2 Unified Mapped RAM/Cache Flexible RAM/Cache Allocation

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ARM926EJ-S MPU Core

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Support for 32-Bit and 16-Bit Thumb® Mode Instruction Sets

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DSP Instruction Extensions and Single Cycle MAC

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ARM® Jazelle® Technology

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EmbeddedICE-RT™ Logic for Real-Time Debug

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ARM9 Memory Architecture

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16K-Byte Instruction Cache

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8K-Byte Data Cache

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16K-Byte RAM

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16K-Byte ROM

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Emulation Trace Buffer™ ETB11™ With 4-KB Memory for ARM9 Debug

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Endianness: Little Endian for ARM and DSP

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Video Processing Subsystem

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Resize Engine Provides:

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Resize Images From 1/4x to 4x

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Separate Horizontal and Vertical Control

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Back End Provides:

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Hardware On-Screen Display OSD

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4 - 54 MHz DACs for a Combination of

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Composite NTSC/PAL Video

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Luma/Chroma Separate Video S-video

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Component YPbPr or RGB Video Progressive

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Digital Output

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8-/16-Bit YUV or up to 24-Bit RGB

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HD Resolution

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Up to 2 Video Windows

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External Memory Interfaces EMIFs

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32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space 1.8V I/O

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Asynchronous16-Bit-Wide EMIF EMIFA With 128M-Byte Address Reach

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Flash Memory Interfaces

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NOR 8-/16-Bit-Wide Data

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NAND 8-/16-Bit-Wide Data

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Flash Card Interfaces

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Multimedia Card MMC/Secure Digital SD with Secure Data I/O SDIO

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CompactFlash Controller With True IDE Mode

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SmartMedia

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Enhanced Direct-Memory-Access EDMA3 Controller 64 Independent Channels

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Two 64-Bit General-Purpose Timers Each Configurable as Two 32-Bit Timers

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One 64-Bit Watch Dog Timer

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Three UARTs One with RTS and CTS Flow Control

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One Serial Port Interface SPI with Two Chip-Selects

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Master/Slave Inter-Integrated Circuit I2C Bus™

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Audio Serial Port ASP

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I2S

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AC97 Audio Codec Interface

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Standard Voice Codec Interface AIC12

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10/100 Mb/s Ethernet MAC EMAC

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IEEE 802.3 Compliant

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Media Independent Interface MII

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VLYNQ™ Interface FPGA Interface

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Host-Port Interface HPI with 16-Bit Multiplexed Address/Data

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USB Port With Integrated 2.0 PHY

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USB 2.0 High-/Full-Speed 480 Mbps Client

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USB 2.0 High-/Full-/Low-Speed Host Mini-Host, Supporting One External Device

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Three Pulse Width Modulator PWM Outputs

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On-Chip ARM ROM Bootloader RBL to Boot From NAND Flash or UART

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ATA/ATAPI I/F ATA/ATAPI-6 Specification

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Individual Power-Saving Modes for ARM/DSP

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Flexible PLL Clock Generators

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IEEE-1149.1 JTAG Boundary-Scan-Compatible

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Up to 71 General-Purpose I/O GPIO Pins Multiplexed With Other Device Functions

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361-Pin Pb-Free BGA Package ZWT Suffix, 0.8-mm Ball Pitch

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0.09-µm/6-Level Cu Metal Process CMOS

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3.3-V and 1.8-V I/O, 1.2-V Internal

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Applications:

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Digital Media

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Networked Media Encode/Decode

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Video Imaging

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