CD54HC74

具有设置和复位的高速 CMOS 逻辑双路上升沿 D 触发器

The ’HC74 and ’HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

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Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

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Asynchronous Set and Reset

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Complementary Outputs

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Buffered Inputs

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Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25°C

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Fanout Over Temperature Range

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Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

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Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

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Wide Operating Temperature Range . . . –55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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HCT Types

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4.5V to 5.5V Operation

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Direct LSTTL Input Logic Compatibility, VIL = 0.8V Max, VIH = 2V Min

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CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor